Advances in VLSI and embedded systems : select proceedings of AVES 2019 / Zuber Patel, Shilpi Gupta, Nithin Kumar Y.B., editors.
International Conference on Advances in VLSI and Embedded Systems (2019 : Surat, India); Patel, Zuber.; Gupta, Shilpi.; Y. B., Nithin Kumar.
2021
TK7874
Available Online

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Title Advances in VLSI and embedded systems : select proceedings of AVES 2019 / Zuber Patel, Shilpi Gupta, Nithin Kumar Y.B., editors.
Meeting Name International Conference on Advances in VLSI and Embedded Systems (2019 : Surat, India)
ISBN 9789811562297 (electronic bk.)
9811562296 (electronic bk.)
9789811562303 (print)
981156230X
9789811562310 (print)
9811562318
9811562288
9789811562280
DOI https://doi.org/10.1007/978-981-15-6229-7
Imprint Singapore : Springer, [2021]
Language English
Description 1 online resource (306 pages)
Other Standard Identifiers 10.1007/978-981-15-6229-7 doi
10.1007/978-981-15-6
Call Number TK7874
Dewey Decimal Classification 621.39/5
Summary This book presents select peer-reviewed proceedings of the International Conference on Advances in VLSI and Embedded Systems (AVES 2019) held at SVNIT, Surat, Gujarat, India. The book covers cutting-edge original research in VLSI design, devices and emerging technologies, embedded systems, and CAD for VLSI. With an aim to address the demand for complex and high-functionality systems as well as portable consumer electronics, the contents focus on basic concepts of circuit and systems design, fabrication, testing, and standardization. This book can be useful for students, researchers as well as industry professionals interested in emerging trends in VLSI and embedded systems.
Access Note Access limited to authorized users.
Digital File Characteristics text file
PDF
Source of Description Description based on print version record.
Added Author Patel, Zuber.
Gupta, Shilpi.
Y. B., Nithin Kumar.
Series Lecture notes in electrical engineering ; v. 676.
Available in Other Form Advances in VLSI and Embedded Systems : Select Proceedings of AVES 2019.
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Test Time Reduction using Power Aware Dynamic Clock Allocation to Scan Vectors
Impact of Spacers in Raised Source/Drain 14 nm technology node.

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