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001432412 001__ 1432412
001432412 003__ OCoLC
001432412 005__ 20230309003441.0
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001432412 008__ 201107s2021\\\\sz\\\\\\ob\\\\001\0\eng\d
001432412 019__ $$a1200651063$$a1204151681$$a1228639514
001432412 020__ $$a9783030548285$$q(electronic bk.)
001432412 020__ $$a3030548287$$q(electronic bk.)
001432412 020__ $$z3030548279
001432412 020__ $$z9783030548278
001432412 0247_ $$a10.1007/978-3-030-54828-5$$2doi
001432412 035__ $$aSP(OCoLC)1204142847
001432412 040__ $$aEBLCP$$beng$$erda$$epn$$cEBLCP$$dYDX$$dYDXIT$$dOCLCO$$dGW5XE$$dSFB$$dOCLCF$$dUKAHL$$dOCLCQ$$dOCL$$dOCLCQ$$dN$T$$dOCLCQ
001432412 049__ $$aISEA
001432412 050_4 $$aQA76.76.P77$$bH47 2021
001432412 08204 $$a005.3$$223
001432412 1001_ $$aHerdt, Vladimir,$$eauthor.
001432412 24510 $$aEnhanced virtual prototyping :$$bfeaturing RISC-V case studies /$$cVladimir Herdt, Daniel Grosse, Rolf Drechsler.
001432412 264_1 $$aCham, Switzerland :$$bSpringer,$$c[2021]
001432412 300__ $$a1 online resource (257 pages)
001432412 336__ $$atext$$btxt$$2rdacontent
001432412 337__ $$acomputer$$bc$$2rdamedia
001432412 338__ $$aonline resource$$bcr$$2rdacarrier
001432412 504__ $$aIncludes bibliographical references and index.
001432412 5050_ $$aIntroduction -- Preliminaries -- An Open-Source RISC-V Evaluation Platform -- Formal Verification of SystemC-based Designs using Symbolic Simulation -- Coverage-guided Testing for Scalable Virtual Prototype Verification -- Verification of Embedded Software Binaries using Virtual Prototypes -- Validation of Firmware-Based Power Management using Virtual Prototypes -- Register-Transfer Level Correspondence Analysis -- Conclusion -- Index.
001432412 506__ $$aAccess limited to authorized users.
001432412 520__ $$aThis book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects. Provides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow Includes automated formal verification methods and advanced coverage-guided testing techniques, tailored for SystemC-based VPs Describes efficient, coverage-guided test generation methods for VP-based functional and non-functional software (SW) analysis and verification Includes correspondence analyses to utilize information between different abstraction levels in the design flow Uses several VP and SW verification case-studies that target the modern RISC-V ISA.
001432412 588__ $$aOnline resource; title from digital title page (viewed on December 30, 2020).
001432412 650_0 $$aSoftware prototyping.
001432412 655_0 $$aElectronic books.
001432412 7001_ $$aGrosse, Daniel,$$eauthor.
001432412 7001_ $$aDrechsler, Rolf,$$eauthor.
001432412 77608 $$iPrint version:$$aHerdt, Vladimir.$$tEnhanced Virtual Prototyping : Featuring RISC-V Case Studies.$$dCham : Springer International Publishing AG, ©2020$$z9783030548278
001432412 852__ $$bebk
001432412 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-030-54828-5$$zOnline Access$$91397441.1
001432412 909CO $$ooai:library.usi.edu:1432412$$pGLOBAL_SET
001432412 980__ $$aBIB
001432412 980__ $$aEBOOK
001432412 982__ $$aEbook
001432412 983__ $$aOnline
001432412 994__ $$a92$$bISE