Technology mapping for LUT-based FPGA / Marcin Kubica, Adam Opara, Dariusz Kania.
Kubica, Marcin author.; Opara, Adam, author.; Kania, Dariusz, author.
2021
TK7895.G36
Available Online

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Title
Technology mapping for LUT-based FPGA / Marcin Kubica, Adam Opara, Dariusz Kania.
Author
Kubica, Marcin author.
ISBN
9783030604882 electronic book
3030604888 electronic book
9783030604875 hardcover
DOI
https://doi.org/10.1007/978-3-030-60488-2
Published
Cham, Switzerland : Springer, [2021]
Copyright
©2021
Language
English
Description
1 online resource (ix, 207 pages) : illustrations (some color).
Item Number
10.1007/978-3-030-60488-2 doi
Call Number
TK7895.G36
Dewey Decimal Classification
621.39/5
Summary
This book covers selected topics of automated logic synthesis dedicated to FPGAs. The authors focused on two main problems: decomposition of the multioutput functions and technology mapping. Additionally, the idea of using binary decision diagrams (BDD) in these processes was presented. The book is a scientific monograph summarizing the authors' many years of research. As a result, it contains a large number of experimental results, which makes it a valuable source for other researchers. The book has a significant didactic value. Its arrangement allows for a gradual transition from basic things (e.g., description of logic functions) to much more complex issues. This approach allows less advanced readers to better understand the described problems. In addition, the authors made sure that the issues described in the book were supported by practical examples, thanks to which the reader can independently analyze even the most complex problems described in the book.
Bibliography, etc. Note
Includes bibliographical references and index.
Access Note
Access limited to authorized users.
Digital File Characteristics
text file PDF
Source of Description
Description based on print version record.
Added Author
Opara, Adam, author.
Kania, Dariusz, author.
Series
Lecture notes in electrical engineering ; v. 713.
Available in Other Form
Technology mapping for LUT-based FPGA.
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Introduction
Methods for representing Boolean functions : basic definitions
Binary decision diagrams
Theoretical basis of decomposition
Decomposition of functions described using BDD
Ordering variables in BDD diagrams
Nondisjoint decomposition
Decomposition of multioutput functions described using BDD
Partial sharing of logic resources
Ability of the configuration of configurable logic blocks
Technology mapping of logic functions in LUT blocks
Technology mapping of logic functions in complex logic blocks
Decomposition methods of FSM implementation
Algorithms for decomposition and technological mapping
Results of experiments
Summary.

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