@article{1433226,
      author = {Soni, Deepraj, and Basu, Kanad, and Nabeel, Mohammed, and  Aaraj, Najwa, and Manzano, Marc, and Karri, Ramesh,},
      url = {http://library.usi.edu/record/1433226},
      title = {Hardware architectures for post-quantum digital signature  schemes /},
      abstract = {This book explores C-based design, implementation, and  analysis of post-quantum cryptography (PQC) algorithms for  signature generation and verification. The authors  investigate NIST round 2 PQC algorithms for signature  generation and signature verification from a hardware  implementation perspective, especially focusing on C-based  design, power-performance-area-security (PPAS) trade-offs  and design flows targeting FPGAs and ASICs. Describes a  comprehensive set of synthesizable c code base as well as  the hardware implementations for the different types of PQC  algorithms including lattice-based, code-based, and  multivariate-based; Demonstrates the hardware (FPGA and  ASIC) and hardware-software optimizations and trade-offs of  the NIST round 2 signature-based PQC algorithms; Enables  designers to build hardware implementations that are  resilient to a variety of side-channels.},
      doi = {https://doi.org/10.1007/978-3-030-57682-0},
      recid = {1433226},
      pages = {1 online resource},
}