Hardware architectures for post-quantum digital signature schemes [electronic resource] / Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri.

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Hardware architectures for post-quantum digital signature schemes [electronic resource] / Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri.

9783030576820 (electronic bk.)
3030576825 (electronic bk.)
3030576817
9783030576813

Cham : Springer, 2021.

English

1 online resource

10.1007/978-3-030-57682-0 doi

TK5102.94

005.8/24
621.3815

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.

Includes bibliographical references and index.

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Print version: 9783030576837
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