@article{1433399,
      recid = {1433399},
      author = {Taraate, Vaibbhav.},
      title = {ASIC design and synthesis : RTL design using Verilog /},
      publisher = {Springer,},
      address = {Singapore :},
      pages = {1 online resource},
      year = {2021},
      abstract = {This book describes simple to complex ASIC design  practical scenarios using Verilog. It builds a story from  the basic fundamentals of ASIC designs to advanced RTL  design concepts using Verilog. Looking at current trends of  miniaturization, the contents provide practical information  on the issues in ASIC design and synthesis using Synopsys  DC and their solution. The book explains how to write  efficient RTL using Verilog and how to improve design  performance. It also covers architecture design strategies,  multiple clock domain designs, low-power design techniques,  DFT, pre-layout STA and the overall ASIC design flow with  case studies. The contents of this book will be useful to  practicing hardware engineers, students, and hobbyists  looking to learn about ASIC design and synthesis.},
      url = {http://library.usi.edu/record/1433399},
      doi = {https://doi.org/10.1007/978-981-33-4642-0},
}