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001433399 001__ 1433399
001433399 003__ OCoLC
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001433399 019__ $$a1231611296$$a1236328141$$a1238201276
001433399 020__ $$a9789813346420$$q(electronic bk.)
001433399 020__ $$a9813346426$$q(electronic bk.)
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001433399 0247_ $$a10.1007/978-981-33-4642-0$$2doi
001433399 035__ $$aSP(OCoLC)1229972558
001433399 040__ $$aYDX$$beng$$epn$$cYDX$$dEBLCP$$dGW5XE$$dSFB$$dDCT$$dOCLCO$$dOCLCF$$dUKAHL$$dOCL$$dOCLCQ$$dOCLCO$$dOCLCQ
001433399 049__ $$aISEA
001433399 050_4 $$aTK7874.6
001433399 08204 $$a621.3815$$223
001433399 1001_ $$aTaraate, Vaibbhav.
001433399 24510 $$aASIC design and synthesis :$$bRTL design using Verilog /$$cVaibbhav Taraate.
001433399 260__ $$aSingapore :$$bSpringer,$$c2021.
001433399 300__ $$a1 online resource
001433399 336__ $$atext$$btxt$$2rdacontent
001433399 337__ $$acomputer$$bc$$2rdamedia
001433399 338__ $$aonline resource$$bcr$$2rdacarrier
001433399 347__ $$atext file
001433399 347__ $$bPDF
001433399 504__ $$aIncludes bibliographical references and index.
001433399 5050_ $$aIntro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 ASIC Design -- 1.2 Types of ASIC -- 1.3 Abstraction Levels -- 1.4 Design Examples -- 1.5 What We Should Know? -- 1.6 Important Terms Used Throughout Design Cycle -- 1.7 Chapter Summary -- 2 ASIC Design Flow -- 2.1 ASIC Design Flow -- 2.1.1 Logic Design -- 2.1.2 Physical Design -- 2.2 FPGA Design Flow -- 2.3 Examples and Thought Process -- 2.4 Design Challenges -- 2.5 Chapter Summary -- 3 Let Us Build Design Foundation -- 3.1 Combinational Design Elements
001433399 5058_ $$a3.2 Logic Understanding and Use of Construct -- 3.3 Arithmetic Resources and Area -- 3.4 Code Converter -- 3.4.1 Binary to Gray Code Converter -- 3.4.2 Gray to Binary Code Converter -- 3.5 Multiplexers -- 3.6 Cascading Stages of MUX Using Instantiation -- 3.7 Decoders -- 3.8 Encoders -- 3.9 Priority Encoders -- 3.10 Strategies During ASIC Design -- 3.11 Exercises -- 3.12 Chapter Summary -- 4 Sequential Design Concepts -- 4.1 Sequential Design Elements -- 4.2 Let Us Understand Blocking Versus Non-blocking Assignments -- 4.2.1 Blocking Assignments -- 4.2.2 Reordering of the Blocking Assignments
001433399 5058_ $$a4.2.3 Non-blocking Assignments -- 4.2.4 Reordering of the Non-blocking Assignments -- 4.3 Latch-Based Designs -- 4.4 Flip-Flop-Based Designs -- 4.5 Reset Strategies -- 4.5.1 Asynchronous Reset -- 4.5.2 Synchronous Reset -- 4.6 Frequency Divider -- 4.7 Synchronous Design -- 4.8 Asynchronous Design -- 4.9 RTL Design and Verification for Complex Designs -- 4.10 Exercises -- 4.11 Chapter Summary -- 5 Important Design Considerations -- 5.1 Timing Parameters -- 5.2 Metastability -- 5.3 Clock Skew -- 5.3.1 Positive Clock Skew -- 5.3.2 Negative Clock Skew -- 5.4 Slack -- 5.4.1 Setup Slack
001433399 5058_ $$a5.4.2 Hold Slack -- 5.5 Clock Latency -- 5.6 Area for the Design -- 5.7 Speed Requirements -- 5.8 Power Requirements -- 5.9 What Are Design Constraints? -- 5.10 Exercises -- 5.11 Chapter Summary -- 6 Important Considerations for ASIC Designs -- 6.1 Synchronous Design and Considerations -- 6.2 Positive Clock Skew and Impact on Speed -- 6.3 Negative Clock Skew and Impact on the Speed -- 6.4 Clock and Network Latency -- 6.5 Timing Paths in the Design -- 6.5.1 Input to Reg Path -- 6.5.2 Reg to Output Path -- 6.5.3 Reg to Reg Path -- 6.5.4 Input to Output Path -- 6.6 Frequency Calculations
001433399 5058_ $$a6.7 What Is On-Chip Variations -- 6.8 Exercises -- 6.9 Chapter Summary -- 7 Multiple Clock Domain Designs -- 7.1 General Strategies for Multiple Clock Domain Designs -- 7.2 What Are Issues in the Multiple Clock Domain Design -- 7.3 Architecture Design Strategies -- 7.4 Control Path and Synchronization -- 7.4.1 Level or Multiflop Synchronizer -- 7.4.2 Pulse Synchronizers -- 7.4.3 MUX Synchronizer -- 7.5 Challenges in the Multiple Bit Data Transfer -- 7.6 Data Path Synchronizers -- 7.6.1 Handshaking Mechanism -- 7.6.2 FIFO Synchronizer -- 7.6.3 Gray Encoding -- 7.7 Summary and Future Discussions
001433399 506__ $$aAccess limited to authorized users.
001433399 520__ $$aThis book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
001433399 650_0 $$aApplication-specific integrated circuits$$xDesign.
001433399 650_0 $$aVerilog (Computer hardware description language)
001433399 650_6 $$aVerilog (Langage de description de matériel informatique)
001433399 655_0 $$aElectronic books.
001433399 77608 $$iPrint version:$$aTaraate, Vaibbhav.$$tASIC design and synthesis.$$dSingapore : Springer, 2021$$z9813346418$$z9789813346413$$w(OCoLC)1202752318
001433399 852__ $$bebk
001433399 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-981-33-4642-0$$zOnline Access$$91397441.1
001433399 909CO $$ooai:library.usi.edu:1433399$$pGLOBAL_SET
001433399 980__ $$aBIB
001433399 980__ $$aEBOOK
001433399 982__ $$aEbook
001433399 983__ $$aOnline
001433399 994__ $$a92$$bISE