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Table of Contents
Intro
Preface
Contents
About the Editors
Introduction to 5G Telecommunication Network
1 Introduction
2 5G and IoT Circuit Requirements
3 5G Transmission Capacity Requirements
4 Microwave and MmW Transmission
4.1 Requirements
4.2 Spectrum
4.3 Transport Network Topology
4.4 Availability of Spectrum for Public Use
5 5G Networking Requirements
6 mmWave Propagation Models
6.1 Free Space Loss and Path Loss
6.2 Outdoor-to-Indoor (O2I) Penetration Loss
6.3 Coupling Loss Performance Analysis
7 Beamforming
7.1 Baseband or Digital Beamforming
7.2 Analog Beamforming
7.3 Hybrid Beamforming
8 Geometry Metric Performance Analysis
9 Circuit Designer Perspective
9.1 Basic Requirements
References
Various Aspects of MOSFET Technology for 5G Communications
1 Introduction
2 Basics of CMOS Transistor and Scaling
3 5G Circuits and Its Constraints
4 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
4.1 Basic Structure and Operation of MOSFETs
4.2 MOSFET Modeling
5 MOSFET Frequency Response
6 Effect of Scaling on MOSFET Integrated
7 Parasitic
8 Transistor as a Switch
9 Capacitors
10 Inductors
11 Transformers
12 Transmission Lines
13 MOS as a Transconductor
14 Scaling Effects
15 Conclusion
References
CMOS Scaled Architecture and Circuit Choices for 5G
1 Introduction
2 Basic Introduction and Definitions
2.1 Beamforming
2.2 Millimeter Wave (MmWave)
2.3 Phased Array
3 Circuit Choices and Architectures of Fifth 5G
4 Link-Level Requirements
5 Architecture and Circuit Trade-off
6 Frequency Conversion
7 Front-End Blocks
8 Survey of Integrated Phased Arrays
9 Scaled CMOS for 73-GHz Design
10 Transceiver at 22 Nm FinFET CMOS Technology
11 Conclusion
References
Low Noise Amplifiers Designing
1 Low-Noise Amplifier
2 Introduction
3 Noise Figure Basics
3.1 Thermal Noise
3.2 Flicker Noise
4 MOSFET Noise Parameters
4.1 Thermal Noise in MOSFET's
4.2 Design Noise Figure
5 Noise Figure for Multistage Amplifiers
6 Challenges 5G Circuits
6.1 Linearity
7 Popular LNA Circuits for 5G
7.1 Linearity Enhancement Techniques
7.2 Parasitic-Insensitive Linearization LNA
7.3 Noise Canceling Technique
8 Cascode Limitations and Scaling Effects
8.1 Cascode Limitations
8.2 Scaling Effects
9 Neutralized CS Amplifier
9.1 Circuit Implementation
9.2 Design Procedure
10 Double-Neutralized Technique
11 FINFET-A Design Perspective View
11.1 Challenges in MmWave Design
11.2 LNA Design at 22 nm FinFET Architecture
11.3 Design Procedure
11.4 Effect of Pad Capacitances
11.5 Impact of Transformer
11.6 FinFET-Based Intel's 22FFL Process
11.7 Noise Performance
11.8 Region of Operation
11.9 Measured Result
11.10 Linearity Optimization
11.11 Measured Results
Preface
Contents
About the Editors
Introduction to 5G Telecommunication Network
1 Introduction
2 5G and IoT Circuit Requirements
3 5G Transmission Capacity Requirements
4 Microwave and MmW Transmission
4.1 Requirements
4.2 Spectrum
4.3 Transport Network Topology
4.4 Availability of Spectrum for Public Use
5 5G Networking Requirements
6 mmWave Propagation Models
6.1 Free Space Loss and Path Loss
6.2 Outdoor-to-Indoor (O2I) Penetration Loss
6.3 Coupling Loss Performance Analysis
7 Beamforming
7.1 Baseband or Digital Beamforming
7.2 Analog Beamforming
7.3 Hybrid Beamforming
8 Geometry Metric Performance Analysis
9 Circuit Designer Perspective
9.1 Basic Requirements
References
Various Aspects of MOSFET Technology for 5G Communications
1 Introduction
2 Basics of CMOS Transistor and Scaling
3 5G Circuits and Its Constraints
4 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
4.1 Basic Structure and Operation of MOSFETs
4.2 MOSFET Modeling
5 MOSFET Frequency Response
6 Effect of Scaling on MOSFET Integrated
7 Parasitic
8 Transistor as a Switch
9 Capacitors
10 Inductors
11 Transformers
12 Transmission Lines
13 MOS as a Transconductor
14 Scaling Effects
15 Conclusion
References
CMOS Scaled Architecture and Circuit Choices for 5G
1 Introduction
2 Basic Introduction and Definitions
2.1 Beamforming
2.2 Millimeter Wave (MmWave)
2.3 Phased Array
3 Circuit Choices and Architectures of Fifth 5G
4 Link-Level Requirements
5 Architecture and Circuit Trade-off
6 Frequency Conversion
7 Front-End Blocks
8 Survey of Integrated Phased Arrays
9 Scaled CMOS for 73-GHz Design
10 Transceiver at 22 Nm FinFET CMOS Technology
11 Conclusion
References
Low Noise Amplifiers Designing
1 Low-Noise Amplifier
2 Introduction
3 Noise Figure Basics
3.1 Thermal Noise
3.2 Flicker Noise
4 MOSFET Noise Parameters
4.1 Thermal Noise in MOSFET's
4.2 Design Noise Figure
5 Noise Figure for Multistage Amplifiers
6 Challenges 5G Circuits
6.1 Linearity
7 Popular LNA Circuits for 5G
7.1 Linearity Enhancement Techniques
7.2 Parasitic-Insensitive Linearization LNA
7.3 Noise Canceling Technique
8 Cascode Limitations and Scaling Effects
8.1 Cascode Limitations
8.2 Scaling Effects
9 Neutralized CS Amplifier
9.1 Circuit Implementation
9.2 Design Procedure
10 Double-Neutralized Technique
11 FINFET-A Design Perspective View
11.1 Challenges in MmWave Design
11.2 LNA Design at 22 nm FinFET Architecture
11.3 Design Procedure
11.4 Effect of Pad Capacitances
11.5 Impact of Transformer
11.6 FinFET-Based Intel's 22FFL Process
11.7 Noise Performance
11.8 Region of Operation
11.9 Measured Result
11.10 Linearity Optimization
11.11 Measured Results