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001438013 003__ OCoLC
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001438013 019__ $$a1260345051$$a1266810668
001438013 020__ $$a9783030713195$$q(electronic bk.)
001438013 020__ $$a3030713199$$q(electronic bk.)
001438013 020__ $$z3030713180
001438013 020__ $$z9783030713188
001438013 0247_ $$a10.1007/978-3-030-71319-5$$2doi
001438013 035__ $$aSP(OCoLC)1259659822
001438013 040__ $$aYDX$$beng$$epn$$cYDX$$dEBLCP$$dGW5XE$$dOCLCO$$dOCLCF$$dDCT$$dUKAHL$$dN$T$$dOCLCQ$$dOCLCO$$dOCLCQ
001438013 049__ $$aISEA
001438013 050_4 $$aTK7885.7
001438013 08204 $$a621.39/2$$223
001438013 1001_ $$aMehta, Ashok B.
001438013 24510 $$aIntroduction to SystemVerilog /$$cAshok B. Mehta.
001438013 260__ $$aCham :$$bSpringer,$$c2021.
001438013 300__ $$a1 online resource
001438013 336__ $$atext$$btxt$$2rdacontent
001438013 337__ $$acomputer$$bc$$2rdamedia
001438013 338__ $$aonline resource$$bcr$$2rdacarrier
001438013 347__ $$atext file
001438013 347__ $$bPDF
001438013 504__ $$aIncludes bibliographical references and index.
001438013 5050_ $$aIntro -- Foreword -- Preface -- Recommended Books to Supplement the Material Presented in this Book -- Chapters of the Book -- Acknowledgments -- Contents -- List of Figures -- List of Tables -- About the Author -- Chapter 1: Introduction -- 1.1 SystemVerilog Language Evolution -- Chapter 2: Data Types -- 2.1 Integer Data Types -- 2.1.1 Integer, int, longint, shortint, logic, byte, reg -- 2.1.2 Signed Types -- 2.1.3 Bits vs. Bytes -- 2.2 Real Data Types -- 2.2.1 "real" Data-Type Conversion Functions -- 2.3 Nets -- 2.3.1 "wire" and "tri" -- 2.3.2 Unresolved "wire" Type: "uwire."
001438013 5058_ $$a2.3.3 Resolved vs. Unresolved Type -- 2.3.4 "wand" and "triand" -- 2.3.5 "wor" and "trior" -- 2.3.6 "tri0" and "tri1" -- 2.4 Drive Strengths -- 2.5 Variable vs. Net -- 2.6 "var" -- 2.7 Variable and Net Initialization -- 2.8 Static, Automatic, and Local Variables -- 2.8.1 Static vs. Local Variables -- 2.8.2 Automatic vs. Static Variable -- 2.8.3 Variable Lifetimes -- 2.9 Enumerated Types -- 2.9.1 Enumerated-Type Methods -- 2.9.2 Enumerated Type with Ranges -- 2.10 User-Defined Type: Typedef -- 2.11 String Data Type -- 2.11.1 String Operators -- 2.11.2 String Methods -- 2.12 Event Data Type
001438013 5058_ $$a2.12.1 Event Sequencing: wait_order () -- 2.13 Static Casting -- 2.13.1 Bit-Stream Casting -- 2.14 Dynamic Casting -- Chapter 3: Arrays -- 3.1 Packed and Unpacked Arrays -- 3.1.1 2-D Packed Array -- 3.1.2 3-D Packed Array -- 3.1.3 1-D Packed and 1-D Unpacked Array -- 3.1.3.1 Multidimensional Arrays -- 3.1.4 4-D Unpacked Array -- 3.1.5 1-D Packed and 3-D Unpacked Array -- 3.1.6 2-D Packed and 2D-Unpacked Array -- 3.1.7 3-D Packed and 1-D Unpacked Array -- 3.2 Assigning, Indexing, and Slicing of Arrays -- 3.2.1 Packed and Unpacked Arrays as Arguments to Subroutines -- 3.3 Dynamic Arrays
001438013 5058_ $$a3.3.1 Dynamic Arrays -- Resizing -- 3.3.2 Copying of Dynamic Arrays -- 3.3.3 Dynamic Array of Arrays -- 3.4 Associative Arrays -- 3.4.1 Wild Card Index -- 3.4.2 String Index -- 3.4.3 Class Index -- 3.4.4 String Index -- Example -- 3.4.5 Associative Array Methods -- 3.4.6 Associative Array -- Default Value -- 3.4.7 Creating a Dynamic Array of Associative Arrays -- 3.5 Array Manipulation Methods -- 3.5.1 Array Locator Methods -- 3.5.2 Array Ordering Methods -- 3.5.3 Array Reduction Methods -- Chapter 4: Queues -- 4.1 Queue Methods -- 4.2 Queue of SystemVerilog Classes
001438013 5058_ $$a4.3 Queue of Queues: Dynamic Array of Queues -- Chapter 5: Structures -- 5.1 Packed Structure -- 5.2 Unpacked Structure -- 5.3 Structure as Module I/O -- 5.4 Structure as an Argument to Task or Function -- 5.5 Structure Within a Structure -- Chapter 6: Union -- 6.1 Packed and Unpacked Unions -- 6.1.1 Unpacked Unions -- 6.1.2 Tagged Unions -- 6.1.3 Packed Union -- Chapter 7: Packages -- Chapter 8: Class -- 8.1 Basics -- 8.2 Base Class -- 8.3 Extended Class and Inheritance -- 8.3.1 Inheritance Memory Allocation -- 8.4 Class Constructor -- 8.4.1 Base Class Constructor
001438013 506__ $$aAccess limited to authorized users.
001438013 520__ $$aThis book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Systems.
001438013 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed July 28, 2021).
001438013 650_0 $$aSystemVerilog (Computer hardware description language)
001438013 650_6 $$aSystemVerilog (Langage de description de matériel informatique)
001438013 655_0 $$aElectronic books.
001438013 77608 $$iPrint version:$$z3030713180$$z9783030713188$$w(OCoLC)1237632836
001438013 852__ $$bebk
001438013 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-030-71319-5$$zOnline Access$$91397441.1
001438013 909CO $$ooai:library.usi.edu:1438013$$pGLOBAL_SET
001438013 980__ $$aBIB
001438013 980__ $$aEBOOK
001438013 982__ $$aEbook
001438013 983__ $$aOnline
001438013 994__ $$a92$$bISE