001438155 000__ 05299cam\a2200697\i\4500
001438155 001__ 1438155
001438155 003__ OCoLC
001438155 005__ 20230309004251.0
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001438155 008__ 210717s2021\\\\sz\a\\\\o\\\\\101\0\eng\d
001438155 019__ $$a1261365657
001438155 020__ $$a9783030816414$$q(electronic bk.)
001438155 020__ $$a3030816419$$q(electronic bk.)
001438155 020__ $$z9783030816407
001438155 020__ $$z3030816400
001438155 0247_ $$a10.1007/978-3-030-81641-4$$2doi
001438155 035__ $$aSP(OCoLC)1260340414
001438155 040__ $$aYDX$$beng$$erda$$epn$$cYDX$$dGW5XE$$dEBLCP$$dOCLCO$$dOCLCF$$dOCLCQ$$dCOM$$dOCLCO$$dOCLCQ
001438155 049__ $$aISEA
001438155 050_4 $$aTK7874.75$$bI45 2020
001438155 08204 $$a621.39/5$$223
001438155 1112_ $$aIFIP/IEEE International Conference on Very Large Scale Integration$$n(28th :$$d2020 :$$cOnline)
001438155 24510 $$aVLSI-SoC design trends :$$b28th IFIP WG 10.5/IEEE International Conference on Very Large Scale, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020 : revised and extended selected papers /$$cAndrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis (eds.).
001438155 24630 $$aVLSI-SoC 2020
001438155 264_1 $$aCham :$$bSpringer,$$c[2021]
001438155 264_4 $$c©2021
001438155 300__ $$a1 online resource :$$billustrations (chiefly color)
001438155 336__ $$atext$$btxt$$2rdacontent
001438155 337__ $$acomputer$$bc$$2rdamedia
001438155 338__ $$aonline resource$$bcr$$2rdacarrier
001438155 4901_ $$aIFIP advances in information and communication technology,$$x1868-4238 ;$$v621
001438155 500__ $$aIncludes author index.
001438155 5050_ $$aLow-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22nm FDSOI -- A 125 pJ/b Mixed-Mode MCMC MIMO Detector with Relaxed DSP -- Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring -- Fully-Autonomous SoC Synthesis using Customizable Cell-Based Analog and Mixed-signal Circuits Generation -- Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform -- SAT-Based Mapping of Data-Flow Graph onto Coarse-Grained Reconfigurable Array -- Learning Based Timing Closure on Relative Timed Design -- Multilevel Signalling for High-Speed Chiplet-to-Chiplet Communication -- From Informal Specifications to an ABV Framework for Industrial Firmware Verification -- Modular Functional Testing: Targeting the Small Embedded Memories in GPUs -- RAT: A Lightweight Architecture Independent System-level Soft Error Mitigation Technique -- SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption -- 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs -- 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model -- Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics -- A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.
001438155 506__ $$aAccess limited to authorized users.
001438155 520__ $$aThis book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.
001438155 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed July 29, 2021).
001438155 650_0 $$aIntegrated circuits$$xVery large scale integration$$vCongresses.
001438155 650_0 $$aSystems on a chip$$vCongresses.
001438155 650_0 $$aComputer network architectures$$vCongresses.
001438155 650_0 $$aInternet of things$$vCongresses.
001438155 650_6 $$aCircuits intégrés à très grande échelle$$vCongrès.
001438155 650_6 $$aSystèmes sur une puce$$vCongrès.
001438155 650_6 $$aRéseaux d'ordinateurs$$xArchitectures$$vCongrès.
001438155 650_6 $$aInternet des objets$$vCongrès.
001438155 655_7 $$aConference papers and proceedings.$$2fast$$0(OCoLC)fst01423772
001438155 655_7 $$aConference papers and proceedings.$$2lcgft
001438155 655_7 $$aActes de congrès.$$2rvmgf
001438155 655_0 $$aElectronic books.
001438155 7001_ $$aCalimera, Andrea,$$eeditor.
001438155 7001_ $$aGaillardon, Pierre-Emmanuel,$$eeditor.
001438155 7001_ $$aKorgaonkar, Kunal,$$eeditor.
001438155 7001_ $$aKvatinsky, Shahar,$$eeditor.
001438155 7001_ $$aReis, Ricardo A. L.$$q(Ricardo Augusto da Luz),$$eeditor.
001438155 830_0 $$aIFIP advances in information and communication technology ;$$v621.$$x1868-4238
001438155 852__ $$bebk
001438155 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-030-81641-4$$zOnline Access$$91397441.1
001438155 909CO $$ooai:library.usi.edu:1438155$$pGLOBAL_SET
001438155 980__ $$aBIB
001438155 980__ $$aEBOOK
001438155 982__ $$aEbook
001438155 983__ $$aOnline
001438155 994__ $$a92$$bISE