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001441877 001__ 1441877
001441877 003__ OCoLC
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001441877 019__ $$a1296677779$$a1296911609$$a1296945070$$a1303719992
001441877 020__ $$a9783662640531$$q(electronic bk.)
001441877 020__ $$a3662640538$$q(electronic bk.)
001441877 020__ $$z9783662640524
001441877 020__ $$z366264052X
001441877 0247_ $$a10.1007/978-3-662-64053-1$$2doi
001441877 035__ $$aSP(OCoLC)1298393247
001441877 040__ $$aEBLCP$$beng$$epn$$cEBLCP$$dGW5XE$$dYDX$$dN$T$$dOCLCO$$dOCLCF$$dOCLCQ
001441877 049__ $$aISEA
001441877 050_4 $$aTL3000
001441877 08204 $$a629.46$$223
001441877 24502 $$aA combined data and power management infrastructure :$$bfor small satellites /$$cJens Eickhoff, editors.
001441877 250__ $$a2nd ed.
001441877 260__ $$aBerlin, Germany :$$bSpringer,$$c2021.
001441877 300__ $$a1 online resource (459 pages)
001441877 336__ $$atext$$btxt$$2rdacontent
001441877 337__ $$acomputer$$bc$$2rdamedia
001441877 338__ $$aonline resource$$bcr$$2rdacarrier
001441877 4901_ $$aSpringer Aerospace Technology
001441877 500__ $$a6.1 Introduction.
001441877 504__ $$aIncludes bibliographical references and index.
001441877 5050_ $$aIntro -- Foreword by Robin Biesbroek -- Foreword by Ana Ambrosio -- Foreword by Olivier L. de Weck -- Foreword by René Laufer -- Foreword by Peter Martinez -- Preface -- Donation for Life -- Contents -- List of Abbreviations -- 1 System Design Concept -- 1.1 Introduction -- 1.2 The Onboard Computer Concept -- 1.3 The PCDU with Enhanced Functionality -- 1.4 CPU-Board Reconfiguration Control -- 1.4.1 Component Functions During Failure Handling -- 1.4.2 A Combined Controller for PCDU and CPU FDIR -- 1.4.3 Failure Management with the Combined-Controller
001441877 5058_ $$a1.4.4 Advantages of the Combined-Controller Approach -- 1.5 CDPI Software Functions -- 1.5.1 Software Initialization -- 1.5.2 SpaceWire Network Initialization and FDIR -- 1.5.3 Remote-Board Reconfiguration Management -- 1.6 Firmware Functions -- 1.6.1 Pulse per Second Signal Management -- 1.6.2 I/O-Board Interface Operation and Group Tailoring -- 1.6.3 Ground/Space Communication -- 1.7 Board Identification -- 1.8 Completeness of System Architecture -- 1.9 Outlook for Future Missions -- 2 OBC CPU-Boards -- 2.1 Introduction -- 2.2 GR712RC-SBC -- 2.2.1 Board Block Diagram -- 2.2.2 Processor
001441877 5058_ $$a2.2.3 Memory -- 2.2.4 Interface Circuits -- 2.2.5 Auxiliary Circuits -- 2.2.6 Mechanical Layout and Constraints -- 2.2.7 PCB Design and Constraints -- 2.2.8 Housing and Connectors -- 2.2.9 Components -- 3 OBC Periphery Boards -- 3.1 Common Design for SpaceWire Routers, I/O and CCSDS-Boards -- 3.2 OBC Periphery Boards Overview -- 3.3 FPGA-Mezzanine -- 3.3.1 FPGA -- 3.3.2 Memory -- 3.3.3 FPGA Configuration -- 3.4 Carrier -- 3.4.1 JTAG -- 3.4.2 Configurable IO -- 3.4.3 SpaceWire -- 3.4.4 Ethernet -- 3.5 System Architecture -- 3.5.1 Board Implementation -- 3.5.2 System Grounding -- 3.5.3 Power Budget
001441877 5058_ $$a3.5.4 Physical Structure -- 3.5.5 Loki-Board IO Connectors -- 3.5.6 Loki-Board Radiation Characteristic -- 3.5.7 Loki-Board Temperature Limits -- 4 SpaceWire Router Boards -- 4.1 SpaceWire Routers for Ground and Flight -- 4.2 General Router Functions -- 4.3 Router Board Structure -- 4.4 Peripherals -- 4.4.1 Peripheral Identification & Configuration (PID) -- 4.4.2 Memory and Applications -- 4.4.3 SpaceWire Ports -- 4.4.4 SpaceWire-Ethernet Bridge -- 4.4.5 FPGA Resources -- 4.4.6 Configuration -- 4.4.7 PPS Interfaces -- 4.5 Router-Board Programmers Model -- 4.5.1 RMAP0
001441877 5058_ $$a4.5.2 Router Configuration Space -- 4.5.3 Port0 RMAP SpaceWire Codec -- 4.5.4 Port0 RMAP PPS -- 4.5.5 MRAM -- 4.5.6 Ethernet -- 5 I/O-Boards -- 5.1 General I/O-Board Functions -- 5.2 I/O Board Structure -- 5.3 Memory and Applications -- 5.4 Peripherals -- 5.4.1 I/O-Board Internal Router -- 5.4.2 SpaceWire Ports -- 5.4.3 UART Interfaces -- 5.4.4 GPIO Interfaces -- 5.5 I/O Board Programmers Model -- 5.5.1 RMAP0 -- 5.5.2 Router Configuration Space -- 5.5.3 SpaceWire Codec -- 5.5.4 MRAM -- 5.5.5 Configurable I/O Interfaces -- 5.5.6 UART -- 5.5.7 GPIO -- 6 CCSDS Decoder/Encoder Boards
001441877 506__ $$aAccess limited to authorized users.
001441877 520__ $$aThis book describes the development and design of a unique combined data and power management infrastructure for small satellites. This new edition became necessary because in the frame of the system's impressive evolution from an academic prototype to one of today's most advanced core avionics, many elements were upgraded to their next technology generation and diverse new components complement the upgraded design. All elements are presented in updated respectively new chapters. This modular infrastructure was selected by the Swiss start-up ClearSpace SA for ESA's first mission ClearSpace-1 to remove space debris. Furthermore it is the baseline for the Thai national satellite development program and is used by an increasing number of universities worldwide for research studies.
001441877 650_0 $$aArtificial satellites$$xElectronic equipment.
001441877 650_0 $$aArtificial satellites$$xControl systems.
001441877 650_6 $$aSatellites artificiels$$xÉquipement électronique.
001441877 650_6 $$aSatellites artificiels$$xSystèmes de commande.
001441877 655_0 $$aElectronic books.
001441877 7001_ $$aEickhoff, Jens,$$eeditor$$1https://isni.org/isni/0000000116666091
001441877 77608 $$iPrint version:$$aEickhoff, Jens.$$tA Combined Data and Power Management Infrastructure.$$dBerlin, Heidelberg : Springer Berlin / Heidelberg, ©2022$$z9783662640524
001441877 830_0 $$aSpringer aerospace technology.
001441877 852__ $$bebk
001441877 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-662-64053-1$$zOnline Access$$91397441.1
001441877 909CO $$ooai:library.usi.edu:1441877$$pGLOBAL_SET
001441877 980__ $$aBIB
001441877 980__ $$aEBOOK
001441877 982__ $$aEbook
001441877 983__ $$aOnline
001441877 994__ $$a92$$bISE