Blocks, towards energy-efficient, coarse-grained reconfigurable architectures / Mark Wijtvliet, Henk Corporaal, Akash Kumar.
Wijtvliet, Mark, author.; Corporaal, Henk, author.; Kumar, Akash, author.
2022
QA76.9.A3 W55 2022
Available Online

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Title Blocks, towards energy-efficient, coarse-grained reconfigurable architectures / Mark Wijtvliet, Henk Corporaal, Akash Kumar.
Author Wijtvliet, Mark, author.
ISBN 9783030797744 (electronic bk.)
3030797740 (electronic bk.)
9783030797737
3030797732
DOI https://doi.org/10.1007/978-3-030-79774-4
Published Cham : Springer, [2022]
Copyright ©2022
Language English
Description 1 online resource (225 pages) : illustrations (chiefly color)
Item Number 10.1007/978-3-030-79774-4 doi
Call Number QA76.9.A3 W55 2022
Dewey Decimal Classification 004.2/2
Summary This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals. Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs; Offers a new view on the positioning of CGRAs; Provides an in-depth description of structure of the Blocks CGRA and its unique aspects; Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches; Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model.
Bibliography, etc. Note Includes bibliographical references and index.
Access Note Access limited to authorized users.
Source of Description Description based on print version record.
Added Author Corporaal, Henk, author.
Kumar, Akash, author.
Available in Other Form Blocks, Towards Energy-Efficient, Coarse-grained Reconfigurable Architectures.
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Introduction
CGRA background
Concept of the Blocks architecture
The Blocks framework
Energy, area, and performance evaluation
Architectural model
Case study: the BrainSense platform
Conclusion.

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