Digital logic design using Verilog : coding and RTL synthesis / Vaibbhav Taraate.
Taraate, Vaibbhav, author.
2022
TK7868.L6 T37 2022eb
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Title
Digital logic design using Verilog : coding and RTL synthesis / Vaibbhav Taraate.
Author
Taraate, Vaibbhav, author.
Edition
Second edition.
ISBN
9789811631993 (electronic bk.)
9811631999 (electronic bk.)
9789811631986
9811631980
DOI
https://doi.org/10.1007/978-981-16-3199-3
Published
Singapore : Springer, [2022]
Copyright
©2022
Language
English
Description
1 online resource : illustrations (chiefly color)
Item Number
10.1007/978-981-16-3199-3 doi
Call Number
TK7868.L6 T37 2022eb
Dewey Decimal Classification
621.39/5
Summary
This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.
Bibliography, etc. Note
Includes bibliographical references and index.
Access Note
Access limited to authorized users.
Digital File Characteristics
text file
PDF
Source of Description
Online resource; title from PDF title page (SpringerLink, viewed November 5, 2021).
Available in Other Form
Digital logic design using Verilog.
Linked Resources
Online Access
Record Appears in
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All Resources
Introduction
Combinational Logic Design (Part I)
Combinational Logic Design (Part II)
Combinational Design Guidelines
Sequential Logic Design
Sequential Design Guidelines
Complex Designs using Verilog RTL
Finite State Machines
Simulation Concepts and PLD Based Designs
RTL Synthesis
Static Timing Analysis (STA)
Constraining Design
Multiple Clock Domain Designs
Low Power Design
RTL Design for SOCs.

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