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001442626 001__ 1442626
001442626 003__ OCoLC
001442626 005__ 20230310003427.0
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001442626 008__ 211104s2022\\\\si\a\\\\ob\\\\001\0\eng\d
001442626 019__ $$a1283138309$$a1283849753$$a1287769008$$a1296665676$$a1346770389
001442626 020__ $$a9789811631993$$q(electronic bk.)
001442626 020__ $$a9811631999$$q(electronic bk.)
001442626 020__ $$z9789811631986
001442626 020__ $$z9811631980
001442626 0247_ $$a10.1007/978-981-16-3199-3$$2doi
001442626 035__ $$aSP(OCoLC)1282597525
001442626 040__ $$aYDX$$beng$$erda$$epn$$cYDX$$dGW5XE$$dEBLCP$$dDCT$$dOCLCF$$dOCLCO$$dDKU$$dOCLCQ$$dCOM$$dOCLCO$$dN$T$$dOCLCQ
001442626 049__ $$aISEA
001442626 050_4 $$aTK7868.L6$$bT37 2022eb
001442626 08204 $$a621.39/5$$223/eng/20221006
001442626 1001_ $$aTaraate, Vaibbhav,$$eauthor.
001442626 24510 $$aDigital logic design using Verilog :$$bcoding and RTL synthesis /$$cVaibbhav Taraate.
001442626 250__ $$aSecond edition.
001442626 264_1 $$aSingapore :$$bSpringer,$$c[2022]
001442626 264_4 $$c©2022
001442626 300__ $$a1 online resource :$$billustrations (chiefly color)
001442626 336__ $$atext$$btxt$$2rdacontent
001442626 337__ $$acomputer$$bc$$2rdamedia
001442626 338__ $$aonline resource$$bcr$$2rdacarrier
001442626 347__ $$atext file
001442626 347__ $$bPDF
001442626 504__ $$aIncludes bibliographical references and index.
001442626 5050_ $$aIntroduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
001442626 506__ $$aAccess limited to authorized users.
001442626 520__ $$aThis second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.
001442626 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed November 5, 2021).
001442626 650_0 $$aLogic design$$xData processing.
001442626 650_0 $$aVerilog (Computer hardware description language)
001442626 650_6 $$aStructure logique$$xInformatique.
001442626 650_6 $$aVerilog (Langage de description de matériel informatique)
001442626 655_0 $$aElectronic books.
001442626 77608 $$iPrint version:$$aTaraate, Vaibbhav.$$tDigital logic design using Verilog.$$bSecond edition.$$dSingapore : Springer, [2022]$$z9811631980$$z9789811631986$$w(OCoLC)1250305442
001442626 852__ $$bebk
001442626 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-981-16-3199-3$$zOnline Access$$91397441.1
001442626 909CO $$ooai:library.usi.edu:1442626$$pGLOBAL_SET
001442626 980__ $$aBIB
001442626 980__ $$aEBOOK
001442626 982__ $$aEbook
001442626 983__ $$aOnline
001442626 994__ $$a92$$bISE