Digital logic design using Verilog : coding and RTL synthesis / Vaibbhav Taraate.

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Digital logic design using Verilog : coding and RTL synthesis / Vaibbhav Taraate.

Second edition.

9789811631993 (electronic bk.)
9811631999 (electronic bk.)
9789811631986
9811631980

Singapore : Springer, [2022]

©2022

English

1 online resource : illustrations (chiefly color)

10.1007/978-981-16-3199-3 doi

TK7868.L6 T37 2022eb

621.39/5

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.

Includes bibliographical references and index.

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Online resource; title from PDF title page (SpringerLink, viewed November 5, 2021).

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