@article{1447577,
      recid = {1447577},
      author = {Kahng, Andrew B., and Lienig, Jens. and Markov, Igor L.  and Hu, Jin.},
      title = {VLSI physical design : from graph partitioning to timing  closure /},
      publisher = {Springer,},
      address = {Cham :},
      pages = {1 online resource (329 pages)},
      year = {2022},
      abstract = {Design and optimization of integrated circuits are  essential to the creation of new semiconductor chips, and  physical optimizations are becoming more prominent as a  result of semiconductor scaling. Modern chip design has  become so complex that it is largely performed by  specialized software, which is frequently updated to  address advances in semiconductor technologies and  increased problem complexities. A user of such software  needs a high-level understanding of the underlying  mathematical models and algorithms. On the other hand, a  developer of such software must have a keen understanding  of computer science aspects, including algorithmic  performance bottlenecks and how various algorithms operate  and interact. "VLSI Physical Design: From Graph  Partitioning to Timing Closure" introduces and compares  algorithms that are used during the physical design phase  of integrated-circuit design, wherein a geometric chip  layout is produced starting from an abstract circuit  design. The emphasis is on essential and fundamental  techniques, ranging from hypergraph partitioning and  circuit placement to timing closure},
      url = {http://library.usi.edu/record/1447577},
      doi = {https://doi.org/10.1007/978-3-030-96415-3},
}