Technology advancement on SoC design : 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, revised and extended selected papers / Victor Grimblatt, Chip Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera (eds.).
IFIP TC10/WG10.5 International Conference on Very Large Scale Integration (29th : 2021 : Online); Grimblatt, Victor, editor.; Chang, Chip-Hong, editor.; Reis, Ricardo A. L. (Ricardo Augusto da Luz), editor.; Chattopadhyay, Anupam, editor.; Calimera, Andrea, editor.
2022
TK7895.E42
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Title Technology advancement on SoC design : 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, revised and extended selected papers / Victor Grimblatt, Chip Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera (eds.).
Meeting Name IFIP TC10/WG10.5 International Conference on Very Large Scale Integration (29th : 2021 : Online)
ISBN 9783031168185 (electronic bk.)
3031168186 (electronic bk.)
3031168178
9783031168178
DOI https://doi.org/10.1007/978-3-031-16818-5
Published Cham : Springer, 2022.
Language English
Description 1 online resource : illustrations.
Item Number 10.1007/978-3-031-16818-5 doi
Call Number TK7895.E42
Dewey Decimal Classification 006.2/2
Summary This book contains extended and revised versions of the best papers presented at the 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, held in Singapore, in October 2021*. The 12 full papers included in this volume were carefully reviewed and selected from the 44 papers (out of 75 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.
Note Selected conference papers.
Bibliography, etc. Note References -- Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level -- 1 Introduction -- 2 Related Work -- 3 Preliminary Definitions -- 4 Methodology -- 4.1 Trace Extraction -- 4.2 Cone of Influence Generation -- 4.3 Instruction Clustering -- 5 Bug Explanation with Temporal Assertions -- 5.1 Time Flow -- 5.2 Trace Extraction -- 5.3 Trace Decoration -- 6 Experimental Results -- 7 Conclusions -- References -- A DfT Strategy for Detecting Emerging Faults in RRAMs -- 1 Introduction -- 2 Background -- 2.1 Memristive Devices
Access Note Access limited to authorized users.
Added Author Grimblatt, Victor, editor.
Chang, Chip-Hong, editor.
Reis, Ricardo A. L. (Ricardo Augusto da Luz), editor.
Chattopadhyay, Anupam, editor.
Calimera, Andrea, editor.
Series IFIP advances in information and communication technology ; 661.
Available in Other Form Print version: 9783031168178
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On the Efficiency of AdapTTA: an Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets
Low-overhead Early-stopping Policies for Efficient Random Forests Inference on Microcontrollers
Transformative Hardware Design following the Model-Driven Architecture Vision
Exploiting program slicing and instruction clusterization to identify the cause of faulty temporal behaviours at system level
A DfT Strategy for Detecting Emerging Faults in RRAMs
FMEA on Critical Systems: a Cross-layer Approach based on High-Level Models
Design and Mitigation techniques of Radiation induced SEEs on Open-Source Embedded Static RAMs
Design of A Reconfigurable Optical Computing Architecture Using Phase Change Material
END-TRUE: Emerging Nanotechnology-based Double-Throughput True Random Number Generator
A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design
A Regulated Sensing Solution based on a Self-Reference Principle for PCM+OTS Memory Array
An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design.

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