Intro
Foreword to the First Edition by Faraj Aalaei
Foreword to the First Edition by Ashok Soota
Foreword to the First Edition by Walden C. Rhines
Preface to the Second Edition
Praise for the First Edition
Preface to the First Edition
About the Book
Why read this book?
What Problems Does It Solve?
Who is the audience?
What are the prerequisites to reading this book?
Why become a VLSI designer?
Contents
Abbreviations
Chapter 1: Introduction
1.1 Introduction to CMOS VLSI
1.2 Application Areas of SoC
1.3 Trends in VLSI

1.4 System on Chip Complexity
1.5 Integration Trend from Circuit to System on Chip
1.6 Speed of Operation
1.7 Die Size
1.8 Design Methodology
1.9 SoC Design and Development
1.10 Skill Set Required
1.11 EDA Environment
1.12 Challenges in All
Reference
Chapter 2: System on Chip (SoC) Design
2.1 Part 1
2.1.1 System on Chip (SoC)
2.2 Constituents of SoC
2.2.1 Processor Subsystem Cores
2.3 Application-Specific Processors
2.4 Control Processors
2.5 Digital Signal Processors
2.6 Vector Processors
2.6.1 Embedded Memory Core
2.6.2 Analog Cores

2.6.3 Interface Cores
2.6.4 On-Chip Clock Generators, PLLs, and Sensors
2.7 Part 2
2.7.1 SoC Development Life Cycle
2.8 SoC Design Requirements
2.9 Design Strategy
2.10 SoC Design Planning
2.11 System Modeling
2.12 System Module Development Feasibility Study
2.13 IP Design Decisions
2.14 Verification IPs
2.15 Target Technology Decision
2.16 Development Plan
2.17 EDA Tool Plan
2.18 Design Center Infrastructure
2.19 Computational Servers
2.20 Filers
2.21 Workstations
2.22 Backup Servers
2.23 Source Control Server
2.24 Firewalls

2.25 Resource Planning
2.26 SoC Design Flow
2.26.1 SoC Chip High-Level Design Methodology
2.26.2 Digital SoC Core Development Flow
2.26.3 Processor Subsystem Core Design
2.26.4 SoC Integrated Design Flow
2.27 EVM Design Development Flow
2.28 Software Development Flow
2.29 Product Integration Flow
Chapter 3: SoC Constituents
3.1 SoC Constituents
3.1.1 Embedded Processor Subsystem for System on Chip
Choice of Embedded Processors for SoC
Embedded General-Purpose RISC Processors
3.1.2 DSP Processors
3.2 Issues of Hw-Sw Co-Design

3.2.1 Processor Subsystems
3.2.2 Processor Configuration Tools
3.2.3 Processor Development Boards
3.3 Embedded Memories
3.3.1 Types of Memories
3.3.2 Choice of Memories
3.3.3 Memory Compiler and Compiled Memories
3.4 Protocol Blocks
3.5 Mixed Signal Blocks
3.6 Radio Frequency (RF) Control Blocks
3.7 Analog Blocks
3.8 Third-Party IP Cores
3.9 System Software
3.9.1 OSI System Model
Physical Layer (Layer 1)
Data Link Layer (Layer 2)
Network Layer (Layer 3)
Transport Layer (Layer 4)
Session Layer (Layer 5)
Presentation Layer (Layer 6)