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001453288 001__ 1453288
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001453288 019__ $$a1351343942
001453288 020__ $$a9783031153457$$q(electronic bk.)
001453288 020__ $$a3031153456$$q(electronic bk.)
001453288 020__ $$z3031153448
001453288 020__ $$z9783031153440
001453288 0247_ $$a10.1007/978-3-031-15345-7$$2doi
001453288 035__ $$aSP(OCoLC)1351199588
001453288 040__ $$aEBLCP$$beng$$cEBLCP$$dYDX$$dGW5XE$$dOCLCF
001453288 049__ $$aISEA
001453288 050_4 $$aTK7874
001453288 08204 $$a621.3815$$223/eng/20221201
001453288 1001_ $$aRaji, Mohsen.
001453288 24510 $$aLifetime reliability-aware design of integrated circuits /$$cMohsen Raji, Behnam Ghavami.
001453288 260__ $$aCham :$$bSpringer,$$c[2023].
001453288 300__ $$a1 online resource (113 p.)
001453288 500__ $$a5.1 Effect of Timing Yield Optimization
001453288 5050_ $$aIntro -- Preface -- Acknowledgment -- Contents -- Impacts of Process Variations and Aging on Lifetime Reliability of Flip-Flops -- 1 Introduction -- 2 Analysis Methodology -- 2.1 Flip-Flop Topologies Under Study -- 2.2 Timing Parameters of Flip-Flops -- 2.3 Aging Effects -- 2.4 BTI Model -- 2.5 Process Variation Model -- 3 Vth Degradation Analysis Approach -- 4 Timing Yield-Aware Lifetime Reliability Metric -- 5 Experimental Results -- 5.1 Characterization Setup -- 5.2 FF Characterization Results -- 5.3 Aging Impacts on Lifetime Reliability -- 5.4 Power-Delay-Product Comparison of FFs
001453288 5058_ $$a6 Discussion and Conclusions -- References -- Restructuring-Based Lifetime Reliability Improvement of Nanoscale Master-Slave Flip-Flops -- 1 Introduction -- 2 Proposed Lifetime Reliability Improvement Approach -- 2.1 Basic Idea -- 2.2 Technique Application to TGFF -- 2.3 Technique Application to TGFFV2 -- 2.4 Technique Application to WPMS -- 2.5 Technique Application to C2MOS -- 2.6 Transistor Sizing -- 3 Experimental Results -- 3.1 Characterization Setup -- 3.2 Lifetime Reliability Increase -- 3.3 Cost Evaluation -- 4 Conclusion -- References
001453288 5058_ $$aLifetime Reliability Improvement of Pulsed Flip-Flops -- 1 Introduction -- 2 Proposed Lifetime Improvement Approach -- 2.1 Basic Idea -- 2.2 Application of the Technique to HLFF -- 2.3 Application of the Technique to SDFF -- 2.4 Application of Technique to USDFF -- 2.5 Technique Application to XCFF -- 3 Experimental Results -- 3.1 Characterization Setup -- 3.2 FF Characterization Results -- 3.3 Lifetime Reliability of Both Structures -- 3.4 Lifetime Reliability Increase -- 3.5 Cost Evaluation -- 4 Conclusion -- References
001453288 5058_ $$aGate Sizing-Based Lifetime Reliability Improvement of Integrated Circuits -- 1 Introduction -- 2 Proposed Framework -- 2.1 Statistical Gate Delay Model Under the Joint Effects of NBTI and PV -- 2.1.1 Initial Gate Delay Under PV Effects -- 2.1.2 Delay Degradation Under the Joint Effects of NBTI and PV Considering Spatial Correlation -- 2.2 Statistical Circuit-Level Delay Computation Considering the Joint Effects of NBTI and PV -- 2.2.1 Arrival Time Propagation -- 2.2.2 Merging Arrival Times -- 2.3 Incremental Criticality-Based Statistical Gate-Sizing Algorithm -- 3 Experimental Results
001453288 5058_ $$a3.1 Circuit Lifetime Reliability Optimization -- 4 Conclusion -- References -- Joint Timing Yield and Lifetime Reliability Optimization of Integrated Circuits -- 1 Introduction -- 2 Problem Formulation -- 3 Gate-Level Delay Model Under the Joint Effects of NBTI and PV -- 3.1 Initial Gate Delay Under PV -- 3.2 Delay Degradation Under Joint Effects of NBTI and PV -- 4 Gate Sizing Method -- 4.1 First Phase: Initial Delay Optimization -- 4.2 Second Phase: Guardband Optimization -- 4.2.1 Guiding Metrics -- 4.2.2 Multiobjective Ranking -- 5 Experimental Results
001453288 506__ $$aAccess limited to authorized users.
001453288 520__ $$aThis book covers the state-of-the-art research in design of modern electronic systems used in safety-critical applications such as medical devices, aircraft flight control, and automotive systems. The authors discuss lifetime reliability of digital systems, as well as an overview of the latest research in the field of reliability-aware design of integrated circuits. They address modeling approaches and techniques for evaluation and improvement of lifetime reliability for nano-scale CMOS digital circuits, as well as design algorithms that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. In addition to developing lifetime reliability analysis and techniques for clocked storage elements (such as flip-flops), the authors also describe analysis and improvement strategies targeting commercial digital circuits. Provides an easy-to-follow procedure for analyzing lifetime reliability of nano-scale digital circuits; Describes state-of-the art aging- and process variation-aware CAD algorithms; Includes reliability improvement techniques for common clocked storage element.
001453288 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed December 1, 2022).
001453288 650_0 $$aIntegrated circuits$$xDesign.
001453288 650_0 $$aIntegrated circuits$$xReliability.
001453288 655_0 $$aElectronic books.
001453288 7001_ $$aGhavami, Behnam.
001453288 77608 $$iPrint version:$$aRaji, Mohsen$$tLifetime Reliability-Aware Design of Integrated Circuits$$dCham : Springer International Publishing AG,c2022$$z9783031153440
001453288 852__ $$bebk
001453288 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-031-15345-7$$zOnline Access$$91397441.1
001453288 909CO $$ooai:library.usi.edu:1453288$$pGLOBAL_SET
001453288 980__ $$aBIB
001453288 980__ $$aEBOOK
001453288 982__ $$aEbook
001453288 983__ $$aOnline
001453288 994__ $$a92$$bISE