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001453386 001__ 1453386
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001453386 019__ $$a1352975147
001453386 020__ $$a9783031110474$$q(electronic bk.)
001453386 020__ $$a3031110471$$q(electronic bk.)
001453386 020__ $$z3031110463
001453386 020__ $$z9783031110467
001453386 0247_ $$a10.1007/978-3-031-11047-4$$2doi
001453386 035__ $$aSP(OCoLC)1352414505
001453386 040__ $$aYDX$$beng$$cYDX$$dEBLCP$$dGW5XE$$dN$T$$dOCLCF
001453386 049__ $$aISEA
001453386 050_4 $$aTK7874
001453386 08204 $$a621.39/5$$223/eng/20221216
001453386 1001_ $$aBairamkulov, Rassul.
001453386 24510 $$aGraphs in VLSI/$$cRassul Bairamkulov, Eby G. Friedman.
001453386 260__ $$aCham, Switzerland :$$bSpringer,$$c2023.
001453386 300__ $$a1 online resource
001453386 504__ $$aIncludes bibliographical references and index.
001453386 5050_ $$aIntro -- Preface -- Acknowledgments -- Contents -- About the Authors -- 1 Introduction -- 1.1 Precursors of VLSI -- 1.2 The rise of VLSI -- 1.3 Outline of book -- 2 Graph fundamentals -- 2.1 Graph categories -- 2.1.1 Hypergraph -- 2.1.2 Graphs with parallel edges -- 2.1.3 Graphs without parallel edges -- 2.1.4 Weighted graph -- 2.1.5 Directed graph -- 2.2 Inter-graph relationships -- 2.3 Graph exploration -- 2.4 Bipartite graph -- 2.5 Directed acyclic graph -- 2.6 Tree -- 2.7 Common problems in graph theory -- 2.7.1 Pathfinding -- 2.7.1.1 Depth-first search -- 2.7.1.2 Breadth-first search
001453386 5058_ $$a2.7.1.3 Dijkstra's algorithm -- 2.7.1.4 Bellman-Ford -- 2.7.1.5 A* (A-star) algorithm -- 2.7.2 Spanning tree -- 2.7.2.1 Borůvka's algorithm -- 2.7.2.2 Prim's algorithm -- 2.7.2.3 Kruskal's algorithm -- 2.7.2.4 Advanced MST Algorithms -- 2.7.2.5 Steiner tree -- 2.7.3 Graph coloring -- 2.7.4 Topological sorting -- 2.8 Summary -- 3 Graphs in VLSI circuits and systems -- 3.1 Graphs as a VLSI abstraction tool -- 3.2 Register transfer level -- 3.2.1 Register allocation -- 3.2.2 Task scheduling -- 3.2.3 Synchronization -- 3.3 Gate layer -- 3.3.1 Ordered binary decision diagram
001453386 5058_ $$a3.3.2 And-inverter graph -- 3.4 Circuit layer -- 3.4.1 Laplacian matrix of a circuit graph -- 3.5 Physical layer -- 3.5.1 Partitioning -- 3.5.2 Floorplanning -- 3.5.3 Placement -- 3.5.4 Routing -- 3.6 Summary -- 4 Synchronization in VLSI -- 4.1 Graph-based timing analysis -- 4.1.1 Timing constraints in synchronous systems -- 4.1.1.1 Local timing constraints -- 4.1.1.2 Global timing constraints -- Serial data path. -- Reconvergent (parallel) paths. -- Cyclic data paths. -- 4.1.1.3 Constraint graph -- 4.2 Clock skew scheduling -- 4.2.1 Robustness -- 4.2.2 Performance -- 4.2.2.1 Wave pipelining
001453386 5058_ $$a4.2.3 Power -- 4.3 Clock tree synthesis -- 4.3.1 Clock tree topology -- 4.3.2 Clock tree embedding -- 4.3.3 Method of means and medians -- 4.3.4 Deferred merge embedding -- 4.3.5 Elmore delay -- 4.3.6 Bounded skew tree -- 4.3.7 Useful skew tree -- 4.4 Summary -- 5 Circuit analysis -- 5.1 Modified nodal analysis -- 5.2 Iterative numerical methods -- 5.2.1 Domain decomposition -- 5.2.2 ps: [/EMC pdfmark [/Subtype /Span /ActualText (script upper H) /StPNE pdfmark [/StBMC pdfmarkHps: [/EMC pdfmark [/StPop pdfmark [/StBMC pdfmark-matrix -- 5.2.3 Multigrid methods -- 5.3 Non-MNA techniques
001453386 5058_ $$a5.3.1 Scattering parameters -- 5.3.2 Random walks -- 5.3.3 Lattice graph -- 5.4 Summary -- 6 Effective resistance of truncated infinite mesh structures -- 6.1 Historical perspective -- 6.2 Electric potential in an infinite mesh -- 6.3 Electric potential within a truncated infinite mesh -- 6.3.1 Modeling truncation with image -- 6.3.1.1 Half-plane mesh -- 6.3.1.2 Quarter-plane mesh -- 6.3.2 Integral expressions for effective resistance -- 6.4 Closed-form approximation -- 6.5 Model evaluation -- 6.5.1 Accuracy evaluation -- 6.5.2 Computational speed -- 6.6 Conclusions
001453386 506__ $$aAccess limited to authorized users.
001453386 520__ $$aNetworks are pervasive. Very large scale integrated (VLSI) systems are no different, consisting of dozens of interconnected subsystems, hundreds of modules, and many billions of transistors and wires. Graph theory is crucial for managing and analyzing these systems. In this book, VLSI system design is discussed from the perspective of graph theory. Starting from theoretical foundations, the authors uncover the link connecting pure mathematics with practical product development. This book not only provides a review of established graph theoretic practices, but also discusses the latest advancements in graph theory driving modern VLSI technologies, covering a wide range of design issues such as synchronization, power network models and analysis, and interconnect routing and synthesis. Provides a practical introduction to graph theory in the context of VLSI systems engineering; Reviews comprehensively graph theoretic methods and algorithms commonly used during VLSI product development process; Includes a review of novel graph theoretic methods and algorithms for VLSI system design.
001453386 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed December 16, 2022).
001453386 650_0 $$aIntegrated circuits$$xVery large scale integration.
001453386 650_0 $$aGraph theory.
001453386 655_0 $$aElectronic books.
001453386 7001_ $$aFriedman, Eby G.
001453386 77608 $$iPrint version:$$z3031110463$$z9783031110467$$w(OCoLC)1330405061
001453386 852__ $$bebk
001453386 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-031-11047-4$$zOnline Access$$91397441.1
001453386 909CO $$ooai:library.usi.edu:1453386$$pGLOBAL_SET
001453386 980__ $$aBIB
001453386 980__ $$aEBOOK
001453386 982__ $$aEbook
001453386 983__ $$aOnline
001453386 994__ $$a92$$bISE