001454243 000__ 03594cam\a22004577a\4500
001454243 001__ 1454243
001454243 003__ OCoLC
001454243 005__ 20230314003508.0
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001454243 008__ 230131s2023\\\\sz\a\\\\ob\\\\001\0\eng\d
001454243 020__ $$a9783031180231$$q(electronic bk.)
001454243 020__ $$a3031180232$$q(electronic bk.)
001454243 020__ $$z3031180224
001454243 020__ $$z9783031180224
001454243 0247_ $$a10.1007/978-3-031-18023-1$$2doi
001454243 035__ $$aSP(OCoLC)1366220193
001454243 040__ $$aYDX$$beng$$cYDX$$dGW5XE$$dEBLCP$$dN$T
001454243 049__ $$aISEA
001454243 050_4 $$aQA76.9.A73
001454243 08204 $$a004.2/2$$223/eng/20230131
001454243 1001_ $$aGoossens, Bernard,$$eauthor.
001454243 24510 $$aGuide to computer processor architecture:$$ba RISC-V approach, with high-level synthesis /$$cBernard Goossens.
001454243 260__ $$aCham, Switzerland :$$bSpringer,$$c[2023]
001454243 300__ $$a1 online resource :$$billustrations
001454243 4901_ $$aUndergraduate topics in computer science
001454243 504__ $$aIncludes bibliographical references and index.
001454243 5050_ $$aPart I. Single core processors -- 1. Getting Ready -- 2. Building a RISC-V Processor -- 3. Building a Pipelined RISC-V Processor -- 4. Building a RISC-V Processor with a Multi-cycle Pipeline -- 5. Building a RISC-V Processor with a Multiple Hart Pipeline -- Part II. Multiple core processors -- 6. Connecting IPs -- 7. A Multi-core RISC-V Processor -- 8. A Multi-core RISC-V Processor with Multi-hart Cores.
001454243 506__ $$aAccess limited to authorized users.
001454243 520__ $$aThis unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Universite de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.
001454243 650_0 $$aComputer architecture.
001454243 650_0 $$aRISC microprocessors.
001454243 655_0 $$aElectronic books.
001454243 77608 $$iPrint version:$$z3031180224$$z9783031180224$$w(OCoLC)1342984336
001454243 830_0 $$aUndergraduate topics in computer science.
001454243 852__ $$bebk
001454243 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-031-18023-1$$zOnline Access$$91397441.1
001454243 909CO $$ooai:library.usi.edu:1454243$$pGLOBAL_SET
001454243 980__ $$aBIB
001454243 980__ $$aEBOOK
001454243 982__ $$aEbook
001454243 983__ $$aOnline
001454243 994__ $$a92$$bISE