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Verified software : theories, tools and experiments. : 14th International Conference, VSTTE 2022, Trento, Italy, October 17-18, 2022, revised selected papers / Akash Lal, Stefano Tonetta (eds.).

VSTTE (Conference) (14th : 2022 : Trento, Italy); Lal, Akash, editor.; Tonetta, Stefano, editor.
2023
QA76.76.V47
Available Online
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Title
Verified software : theories, tools and experiments. : 14th International Conference, VSTTE 2022, Trento, Italy, October 17-18, 2022, revised selected papers / Akash Lal, Stefano Tonetta (eds.).
Meeting Name
VSTTE (Conference) (14th : 2022 : Trento, Italy)
ISBN
9783031258039 (electronic bk.)
3031258037 (electronic bk.)
9783031258022
DOI
https://doi.org/10.1007/978-3-031-25803-9
Published
Cham : Springer, [2023]
Copyright
©2023
Language
English
Description
1 online resource (viii, 167 pages) : illustrations (some color).
Item Number
10.1007/978-3-031-25803-9 doi
Call Number
QA76.76.V47
Dewey Decimal Classification
005.1/4
Summary
This book constitutes the refereed proceedings of the 14th International Conference on Verified Software. Theories, Tools and Experiments, VSTTE 2022 held in Trento, Italy, during October 17-18, 2022. The 9 papers presented in this volume were carefully reviewed and selected from 20 submissions. The papers describe software verification efforts that involve collaboration, theory unification, tool integration, and formalized domain knowledge as well as novel experiments and case studies evaluating verification techniques and technologies.
Note
International conference proceedings.
Includes author index.
Access Note
Access limited to authorized users.
Source of Description
Online resource; title from PDF title page (SpringerLink, viewed February 6, 2023).
Added Author
Lal, Akash, editor.
Tonetta, Stefano, editor.
Series
Lecture notes in computer science ; 13800.
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Online Access
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All Resources
Compositional Safety LTL Synthesis
Leroy and Blazy were right: their memory model soundness proof is automatable
Shellac: a compiler synthesizer for concurrent programs
A sequentialization procedure for fault-tolerant protocols
Towards Practical Partial Order Reduction for High-Level Formalisms
SMT-based Verification of Persistency Invariants of Px86 Programs
A Formal Semantics for P-Code
Separating Separation Logic - Modular Verification of Red-Black Trees
Residual Runtime Verification via Reachability Analysis.

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