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001458296 020__ $$z9783319305387
001458296 020__ $$a9783319305394 (e-book)
001458296 035__ $$a(MiAaPQ)EBC4526856
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001458296 035__ $$a(CaONFJC)MIL923089
001458296 035__ $$a(OCoLC)948607446
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001458296 050_4 $$aTK7885.7$$b.M448 2016
001458296 0820_ $$a621.392$$223
001458296 1001_ $$aMehta, Ashok B.,$$eauthor.
001458296 24510 $$aSystemVerilog assertions and functional coverage :$$bguide to language, methodology and applications /$$cAshok B. Mehta.
001458296 250__ $$aSecond edition.
001458296 264_1 $$a[Cham], Switzerland :$$bSpringer,$$c2016.
001458296 264_4 $$c2016
001458296 300__ $$a1 online resource (424 pages) :$$billustrations, tables.
001458296 336__ $$atext$$2rdacontent
001458296 337__ $$acomputer$$2rdamedia
001458296 338__ $$aonline resource$$2rdacarrier
001458296 500__ $$aIncludes index.
001458296 506__ $$aAccess limited to authorized users.
001458296 588__ $$aDescription based on print version record.
001458296 650_0 $$aVerilog (Computer hardware description language)
001458296 650_0 $$aElectronic digital computers$$xDesign and construction.
001458296 650_0 $$aIntegrated circuits$$xVerification.
001458296 655_0 $$aElectronic books
001458296 77608 $$iPrint version:$$aMehta, Ashok B.$$tSystemVerilog assertions and functional coverage : guide to language, methodology and applications.$$bSecond edition.$$d[Cham], Switzerland : Springer, c2016 $$z9783319305387 $$w2016932750
001458296 852__ $$bebk
001458296 85640 $$3ProQuest Ebook Central Academic Complete $$uhttps://univsouthin.idm.oclc.org/login?url=https://ebookcentral.proquest.com/lib/usiricelib-ebooks/detail.action?docID=4526856$$zOnline Access
001458296 909CO $$ooai:library.usi.edu:1458296$$pGLOBAL_SET
001458296 980__ $$aBIB
001458296 980__ $$aEBOOK
001458296 982__ $$aEbook
001458296 983__ $$aOnline