Built-in fault-tolerant computing paradigm for resilient large-scale chip design : a self-test, self-diagnosis, and self-repair-based approach / Xiaowei Li, Guihai Yan, Cheng Liu.
Li, Xiaowei.; Yan, Guihai.; Liu, Cheng.
2023
TK7874
Available Online

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Title Built-in fault-tolerant computing paradigm for resilient large-scale chip design : a self-test, self-diagnosis, and self-repair-based approach / Xiaowei Li, Guihai Yan, Cheng Liu.
Author Li, Xiaowei.
ISBN 9789811985515 (electronic bk.)
9811985510 (electronic bk.)
9811985502
9789811985508
DOI https://doi.org/10.1007/978-981-19-8551-5
Publication Details Singapore : Springer, 2023.
Language English
Description 1 online resource (318 p.)
Item Number 10.1007/978-981-19-8551-5 doi
Call Number TK7874
Dewey Decimal Classification 621.39/5
Summary With the end of Dennard scaling and Moores law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or 3S for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.
Access Note Access limited to authorized users.
Source of Description Online resource; title from PDF title page (SpringerLink, viewed March 16, 2023).
Added Author Yan, Guihai.
Liu, Cheng.
Available in Other Form Built-In Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design
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Chapter 1: Introduction
Chapter 2: Fault-tolerant general circuits with 3S
Chapter 3: Fault-tolerant general purposed processors with 3S
Chapter 4: Fault-tolerant network-on-chip with 3S
Chapter 5: Fault-tolerant deep learning processors with 3S
Chapter 6: Conclusion.

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