001461322 000__ 04332cam\a22005657a\4500
001461322 001__ 1461322
001461322 003__ OCoLC
001461322 005__ 20230503003347.0
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001461322 008__ 230311s2023\\\\si\\\\\\o\\\\\000\0\eng\d
001461322 019__ $$a1371686666
001461322 020__ $$a9789811985515$$q(electronic bk.)
001461322 020__ $$a9811985510$$q(electronic bk.)
001461322 020__ $$z9811985502
001461322 020__ $$z9789811985508
001461322 0247_ $$a10.1007/978-981-19-8551-5$$2doi
001461322 035__ $$aSP(OCoLC)1372396638
001461322 040__ $$aEBLCP$$beng$$cEBLCP$$dGW5XE$$dYDX$$dEBLCP$$dUKAHL$$dOCLCF
001461322 049__ $$aISEA
001461322 050_4 $$aTK7874
001461322 08204 $$a621.39/5$$223/eng/20230316
001461322 1001_ $$aLi, Xiaowei.
001461322 24510 $$aBuilt-in fault-tolerant computing paradigm for resilient large-scale chip design :$$ba self-test, self-diagnosis, and self-repair-based approach /$$cXiaowei Li, Guihai Yan, Cheng Liu.
001461322 260__ $$aSingapore :$$bSpringer,$$c2023.
001461322 300__ $$a1 online resource (318 p.)
001461322 5050_ $$aChapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion.
001461322 506__ $$aAccess limited to authorized users.
001461322 520__ $$aWith the end of Dennard scaling and Moores law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or 3S for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.
001461322 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed March 16, 2023).
001461322 650_0 $$aIntegrated circuits$$xLarge scale integration$$xDesign.
001461322 650_0 $$aFault-tolerant computing.
001461322 655_0 $$aElectronic books.
001461322 7001_ $$aYan, Guihai.
001461322 7001_ $$aLiu, Cheng.
001461322 77608 $$iPrint version:$$aLi, Xiaowei$$tBuilt-In Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design$$dSingapore : Springer,c2023$$z9789811985508
001461322 852__ $$bebk
001461322 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-981-19-8551-5$$zOnline Access$$91397441.1
001461322 909CO $$ooai:library.usi.edu:1461322$$pGLOBAL_SET
001461322 980__ $$aBIB
001461322 980__ $$aEBOOK
001461322 982__ $$aEbook
001461322 983__ $$aOnline
001461322 994__ $$a92$$bISE