Speeding-up radio-frequency integrated circuit sizing with neural networks / João L. C. P. Domingues, Pedro J.C.D.C Vaz, António P.L. Gusmão, Nuno C.G. Horta, Nuno C.C. Lourenço, Ricardo M.F. Martins.
Domingues, João L. C. P., author.; Vaz, Pedro J. C. D. C., author.; Gusmão, António P. L., author.; Horta, Nuno C. G., author.; Lourenço, Nuno C. C., author.; Martins, Ricardo (Ferreira Martins), author.
2023
TK7874
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Title Speeding-up radio-frequency integrated circuit sizing with neural networks / João L. C. P. Domingues, Pedro J.C.D.C Vaz, António P.L. Gusmão, Nuno C.G. Horta, Nuno C.C. Lourenço, Ricardo M.F. Martins.
Author Domingues, João L. C. P., author.
ISBN 9783031250996
3031250990
3031250982
9783031250989
DOI https://doi.org/10.1007/978-3-031-25099-6
Publication Details Cham, Switzerland : Springer, 2023.
Language English
Description 1 online resource (viii, 109 pages) : illustrations (chiefly color).
Item Number 10.1007/978-3-031-25099-6 doi
Call Number TK7874
Dewey Decimal Classification 621.3815
Summary In this book, innovative research using artificial neural networks (ANNs) is conducted to automate the sizing task of RF IC design, which is used in two different steps of the automatic design process. The advances in telecommunications, such as the 5th generation broadband or 5G for short, open doors to advances in areas such as health care, education, resource management, transportation, agriculture and many other areas. Consequently, there is high pressure in todays market for significant communication rates, extensive bandwidths and ultralow-power consumption. This is where radiofrequency (RF) integrated circuits (ICs) come in hand, playing a crucial role. This demand stresses out the problem which resides in the remarkable difficulty of RF IC design in deep nanometric integration technologies due to their high complexity and stringent performances. Given the economic pressure for high quality yet cheap electronics and challenging time-to-market constraints, there is an urgent need for electronic design automation (EDA) tools to increase the RF designers productivity and improve the quality of resulting ICs. In the last years, the automatic sizing of RF IC blocks in deep nanometer technologies has moved toward process, voltage and temperature (PVT)-inclusive optimizations to ensure their robustness. Each sizing solution is exhaustively simulated in a set of PVT corners, thus pushing modern workstations capabilities to their limits. Standard ANNs applications usually exploit the models capability of describing a complex, harder to describe, relation between input and target data. For that purpose, ANNs are a mechanism to bypass the process of describing the complex underlying relations between data by feeding it a significant number of previously acquired input/output data pairs that the model attempts to copy. Here, and firstly, the ANNs disrupt from the most recent trials of replacing the simulator in the simulation-based sizing with a machine/deep learning model, by proposing two different ANNs, the first classifies the convergence of the circuit for nominal and PVT corners, and the second predicts the oscillating frequencies for each case. The convergence classifier (CCANN) and frequency guess predictor (FGPANN) are seamlessly integrated into the simulation-based sizing loop, accelerating the overall optimization process. Secondly, a PVT regressor that inputs the circuits sizing and the nominal performances to estimate the PVT corner performances via multiple parallel artificial neural networks is proposed. Two control phases prevent the optimization process from being misled by inaccurate performance estimates. As such, this book details the optimal description of the input/output data relation that should be fulfilled. The developed description is mainly reflected in two of the systems characteristics, the shape of the input data and its incorporation in the sizing optimization loop. An optimal description of these components should be such that the model should produce output data that fulfills the desired relation for the given training data once fully trained. Additionally, the model should be capable of efficiently generalizing the acquired knowledge in newer examples, i.e., never-seen input circuit topologies.
Note Description based upon print version of record.
Bibliography, etc. Note Includes bibliographical references.
Access Note Access limited to authorized users.
Source of Description Description based on print version record.
Added Author Vaz, Pedro J. C. D. C., author.
Gusmão, António P. L., author.
Horta, Nuno C. G., author.
Lourenço, Nuno C. C., author.
Martins, Ricardo (Ferreira Martins), author.
Series SpringerBriefs in applied sciences and technology. Computational intelligence. 2191-5318
Available in Other Form Speeding-Up Radio-Frequency Integrated Circuit Sizing with Neural Networks
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Intro
Preface
Contents
1 Introduction
1.1 Analog/RF Integrated Circuit Design Automation
1.2 Analog IC Design Flow
1.3 Machine Learning and Analog IC Sizing
1.4 Conclusion
References
2 Background and Related Work
2.1 Knowledge-Based Sizing
2.2 Optimization-Based Sizing
2.2.1 Equation-Based Evaluation
2.2.2 Simulation-Based Evaluation
2.3 Machine Learning in Simulation-Based Evaluation
2.3.1 Types of Supervision
2.3.2 Simulation-Based Sizing Enhanced with SVMs
2.3.3 Simulation-Based Sizing Enhanced with ANNs

2.4 Other ML/DL Efforts on Analog/RF Sizing
2.4.1 Predicting Sizing from Performances
2.4.2 Reinforcement Learning
2.5 Case Study
2.5.1 Dual-Mode Class C/D VCO
2.5.2 Dataset Generation
2.6 Conclusion
References
3 Convergence Classifier and Frequency Guess Predictor Based on ANNs
3.1 Contributions
3.2 Classifier and Regressor Based on Deep ANNs
3.2.1 Underlying Architectures
3.3 Training the Model in Isolation (Results Pre-integration)
3.3.1 Dataset Processing
3.3.2 Feature Engineering
3.3.3 Convergence Classifier and Its Hyperparameters

3.3.4 Regressor and Its Hyperparameters
3.3.5 Final Model Details
3.3.6 Discussion
3.4 In-the-Loop Integration
3.4.1 Class C/D VCO for 3.5-to-4.8 GHz @ 50% Threshold
3.4.2 Class C/D VCO for 3.5-to-4.8 GHz @ 75% Threshold
3.4.3 Class C/D VCO for 3.5-to-4.8 GHz @ 90% and 100% Thresholds
3.4.4 Analysis of the Points Fed to the Simulator
3.4.5 Plug-and-Play Class C/D VCO 2.3 GHz-to-2.5 GHz
3.4.6 Plug-and-Train Ultralow-Power Class B/C VCO
3.5 Conclusions and Future Research Directions
3.5.1 Conclusions
3.5.2 Future Work
References

4 Process, Voltage and Temperature Corner Performance Estimator Using ANNs
4.1 Contributions
4.2 Controlled PVT Regressor Based on Deep ANNs
4.3 Training the Model in Isolation (Results Pre-integration)
4.3.1 Dataset Processing
4.3.2 Feature Engineering
4.3.3 Tuning Hyper-Parameters
4.3.4 Final Model Details
4.3.5 Test Results
4.4 In-the-Loop Integration
4.4.1 Class C/D VCO with PVT Estimator Working at 100%
4.4.2 PVT Estimator with Error Controller
4.4.3 Results with Controlled PVT Estimator
4.5 Conclusions and Future Research Directions

4.5.1 Conclusions
4.5.2 Future Work
References

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