Intro
Foreword
Preface
Contents
1 Introduction
2 Physical Unclonable Functions
2.1 Security Properties and Metrics
2.2 Attacker Model
2.3 Modeling Attacks
2.3.1 Machine Learning Attacks
2.3.2 Specialized Attacks
2.3.3 Provable Attacks
2.4 Hardware Security
3 XOR Arbiter PUF
3.1 Arbiter PUF
3.2 XOR Arbiter PUF
3.3 Metrics
3.3.1 Systematic Bias of XOR Arbiter PUFs
3.3.2 Implementation
3.4 Logistic Regression Attack
3.5 Physical Attacks
3.6 Neural Network Attacks
3.6.1 Revisited: Santikellur et al.

3.6.2 Revisited: Aseeri et al.
3.6.3 Revisited: Mursi et al.
3.6.3.1 Neural Network
3.6.3.2 Replication and Results
3.6.3.3 Hyperparameter Optimization
3.6.3.4 Noise Resilience
3.6.3.5 Application to Real-World Data
3.6.4 Comparison
3.7 Arbitrarily Large XOR Arbiter PUFs
3.7.1 Stability
3.7.2 Arbiter PUF
3.7.3 Majority Vote Arbiter PUF
3.7.4 XOR Arbiter PUF
3.7.5 Number of Votes Required
3.7.6 Simulation
3.8 Reliability-Based Attacks
4 XOR Arbiter PUFs with Input Transformation
4.1 Input Transformations: Classic vs. Random

4.1.1 Pseudorandom Input Transformation
4.1.2 Local Minima
4.2 Input Transformations: Lightweight Secure
4.2.1 Feature Vector Correlation
4.2.2 Improved Attack
4.3 Permutation PUF
5 Interpose PUF
5.1 Splitting Attack
5.1.1 Initial Modeling of the Lower Layer via Random Interpose Bits
5.1.2 Modeling of the Upper Layer
5.1.3 Divide-and-Conquer Attack
5.2 Results and Performance Analysis
5.3 Neural Network Splitting Attack
5.4 Variants of the Interpose PUF
5.4.1 Design Details and Motivation
5.4.2 Empirical Results of Deep Learning Modeling Attacks

6 Feed-Forward Arbiter PUF
6.1 Design
6.2 Evolution Strategies Attacks
6.3 Neural Network Attack
7 Beli PUF
7.1 Design
7.2 Model Based on Additive Delay Model
7.3 Implementation and Metrics
7.4 Generic MLP Attack
7.5 Specialized Neural Network Attack
8 LP-PUF
8.1 Design
8.2 Metrics
8.3 Splitting Attack
8.4 Reliability Attack
8.5 MLP Attack
8.6 Limitations
Copyright Notice
A Arbiter PUF Additive Delay Model
B Permutation PUF
Bibliography
Index