Efficient execution of irregular dataflow graphs : hardware/software co-optimization for probabilistic AI and sparse linear algebra / Nimish Shah, Wannes Meert, Marian Verhelst.
Shah, Nimish, author.; Meert, Wannes, author.; Verhelst, Marian, author.
2023
TK7867 .S53 2023
Available Online

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Title
Efficient execution of irregular dataflow graphs : hardware/software co-optimization for probabilistic AI and sparse linear algebra / Nimish Shah, Wannes Meert, Marian Verhelst.
Author
Shah, Nimish, author.
ISBN
9783031331367 electronic book
3031331362 electronic book
9783031331350
3031331354
DOI
https://doi.org/10.1007/978-3-031-33136-7
Published
Cham : Springer, [2023]
Language
English
Description
1 online resource (xxi, 143 pages) : illustrations
Item Number
10.1007/978-3-031-33136-7 doi
Call Number
TK7867 .S53 2023
Dewey Decimal Classification
621.3815028563
Summary
This book focuses on the acceleration of emerging irregular sparse workloads, posed by novel artificial intelligent (AI) models and sparse linear algebra. Specifically, the book outlines several co-optimized hardware-software solutions for a highly promising class of emerging sparse AI models called Probabilistic Circuit (PC) and a similar sparse matrix workload for triangular linear systems (SpTRSV). The authors describe optimizations for the entire stack, targeting applications, compilation, hardware architecture and silicon implementation, resulting in orders of magnitude higher performance and energy-efficiency compared to the existing state-of-the-art solutions. Thus, this book provides important building blocks for the upcoming generation of edge AI platforms. Analyzes the key bottlenecks in the existing platforms for these sparse and irregular AI and linear algebra algorithms; Discusses an emerging set of AI workloads that rely on sparse matrix operations and graph-based computations; Shows how to address the execution challenges of this novel class of algorithms through hardware-software codesign.
Bibliography, etc. Note
Includes bibliographical references and index.
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Access limited to authorized users.
Source of Description
Online resource; title from PDF title page (SpringerLink, viewed July 19, 2023).
Added Author
Meert, Wannes, author.
Verhelst, Marian, author.
Available in Other Form
Print version: 9783031331350
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Chapter 1. Irregular workloads at risk of losing the hardware lottery
Chapter 2. Suitable data representation: A study of fixed point, floating point,and positTM formats for probabilistic AI
Chapter 3. GraphOpt: constrained-optimization-based parallelization of irregular workloads for multicore processors
Chapter 4. DAG Processing Unit version 1 (DPU): Efficient execution of irregular workloads on a multicore processor
Chapter 5. DAG Processing Unit version 2 (DPU-v2): Efficient execution of irregular workloads on a spatial datapath
Chapter 6. Conclusions and future work.

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