001472320 000__ 03972cam\\22006137i\4500
001472320 001__ 1472320
001472320 003__ OCoLC
001472320 005__ 20230908003406.0
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001472320 008__ 230807s2023\\\\sz\a\\\\ob\\\\001\0\eng\d
001472320 019__ $$a1391434198$$a1392344495
001472320 020__ $$a9783031342370$$q(electronic bk.)
001472320 020__ $$a3031342372$$q(electronic bk.)
001472320 020__ $$z9783031342363
001472320 020__ $$z3031342364
001472320 0247_ $$a10.1007/978-3-031-34237-0$$2doi
001472320 035__ $$aSP(OCoLC)1392651859
001472320 040__ $$aGW5XE$$beng$$erda$$epn$$cGW5XE$$dEBLCP$$dYDX$$dN$T
001472320 049__ $$aISEA
001472320 050_4 $$aTK7895.E42
001472320 08204 $$a621.3815$$223/eng/20230807
001472320 1001_ $$aHan, Donghyeon,$$eauthor.
001472320 24510 $$aOn-chip training NPU -- algorithm, architecture and SoC design /$$cDonghyeon Han, Hoi-Jun Yoo.
001472320 264_1 $$aCham :$$bSpringer,$$c2023.
001472320 300__ $$a1 online resource (xxiii, 237 pages) :$$billustrations (some color)
001472320 336__ $$atext$$btxt$$2rdacontent
001472320 337__ $$acomputer$$bc$$2rdamedia
001472320 338__ $$aonline resource$$bcr$$2rdacarrier
001472320 504__ $$aIncludes bibliographical references and index.
001472320 5050_ $$aChapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion.
001472320 506__ $$aAccess limited to authorized users.
001472320 520__ $$aUnlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding.
001472320 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed August 7, 2023).
001472320 650_0 $$aSystems on a chip$$xDesign and construction.
001472320 650_0 $$aIntegrated circuits.
001472320 650_0 $$aNeural networks (Computer science)
001472320 655_0 $$aElectronic books.
001472320 7001_ $$aYoo, Hoi-Jun,$$eauthor.
001472320 77608 $$iPrint version:$$aHan, Donghyeon$$tOn-Chip Training NPU - Algorithm, Architecture and SoC Design$$dCham : Springer,c2023$$z9783031342363
001472320 852__ $$bebk
001472320 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-031-34237-0$$zOnline Access$$91397441.1
001472320 909CO $$ooai:library.usi.edu:1472320$$pGLOBAL_SET
001472320 980__ $$aBIB
001472320 980__ $$aEBOOK
001472320 982__ $$aEbook
001472320 983__ $$aOnline
001472320 994__ $$a92$$bISE