001475781 000__ 02109nam\\2200517\i\4500
001475781 001__ 1475781
001475781 003__ MiAaPQ
001475781 005__ 20231003174617.0
001475781 006__ m\\\\\o\\d\\\\\\\\
001475781 007__ cr\cn\nnnunnun
001475781 008__ 230919s2022\\\\maua\\\\ob\\\\001\0\eng\d
001475781 020__ $$z9781630819101
001475781 020__ $$a9781630819118
001475781 035__ $$a(MiAaPQ)EBC29703387
001475781 035__ $$a(Au-PeEL)EBL29703387
001475781 035__ $$a(OCoLC)1343247599
001475781 040__ $$aMiAaPQ$$beng$$erda$$epn$$cMiAaPQ$$dMiAaPQ
001475781 050_4 $$aTK7874.55$$b.S247 2022
001475781 0820_ $$a621.3815$$223
001475781 1001_ $$aSahrling, Mikael,$$d1964-$$eauthor.
001475781 24510 $$aLayout techniques for integrated circuit designers /$$cMikael Sahrling.
001475781 264_1 $$aNorwood, MA :$$bArtech House,$$c[2022]
001475781 264_4 $$c©2022
001475781 300__ $$a1 online resource (342 pages) :$$billustrations.
001475781 336__ $$atext$$btxt$$2rdacontent
001475781 337__ $$acomputer$$bc$$2rdamedia
001475781 338__ $$aonline resource$$bcr$$2rdacarrier
001475781 504__ $$aIncludes bibliographical references and index.
001475781 506__ $$aAccess limited to authorized users.
001475781 588__ $$aDescription based on print version record.
001475781 650_0 $$aIntegrated circuit layout.
001475781 655_0 $$aElectronic books
001475781 77608 $$iPrint version:$$aSahrling, Mikael, 1964-$$tLayout techniques for integrated circuit designers.$$dNorwood, MA : Artech House, c2022 $$z9781630819101
001475781 852__ $$bebk
001475781 85640 $$3ProQuest Ebook Central Academic Complete $$uhttps://univsouthin.idm.oclc.org/login?url=https://ebookcentral.proquest.com/lib/usiricelib-ebooks/detail.action?docID=29703387$$zOnline Access
001475781 909CO $$ooai:library.usi.edu:1475781$$pGLOBAL_SET
001475781 980__ $$aBIB
001475781 980__ $$aEBOOK
001475781 982__ $$aEbook
001475781 983__ $$aOnline