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001480949 001__ 1480949
001480949 003__ OCoLC
001480949 005__ 20231031003316.0
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001480949 019__ $$a1398279310
001480949 020__ $$a9783031429217$$q(electronic bk.)
001480949 020__ $$a3031429214$$q(electronic bk.)
001480949 020__ $$z9783031429200
001480949 020__ $$z3031429206
001480949 0247_ $$a10.1007/978-3-031-42921-7$$2doi
001480949 035__ $$aSP(OCoLC)1398307897
001480949 040__ $$aGW5XE$$beng$$erda$$epn$$cGW5XE$$dYDX$$dEBLCP$$dOCLCO$$dWSU
001480949 049__ $$aISEA
001480949 050_4 $$aQA76.9.A3
001480949 08204 $$a004$$223/eng/20230920
001480949 1112_ $$aARC (Symposium)$$n(19th :$$d2023 :$$cCottbus, Germany)
001480949 24510 $$aApplied reconfigurable computing :$$barchitectures, tools, and applications : 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings /$$cFrancesca Palumbo, Georgios Keramidas, Nikolaos Voros, Pedro C. Diniz, editors.
001480949 2463_ $$aARC 2023
001480949 264_1 $$aCham :$$bSpringer,$$c2023.
001480949 300__ $$a1 online resource (xiii, 376 pages) :$$billustrations (some color).
001480949 336__ $$atext$$btxt$$2rdacontent
001480949 337__ $$acomputer$$bc$$2rdamedia
001480949 338__ $$aonline resource$$bcr$$2rdacarrier
001480949 4901_ $$aLecture notes in computer science,$$x1611-3349 ;$$v14251
001480949 500__ $$aIncludes author index.
001480949 5050_ $$aDesign Methods and Tools -- High-Level Synthesis of Memory Systems for Decoupled Data Orchestration -- Rapid Prototyping of Complex Micro-architectures through High-Level Synthesis -- NVMulator: A Con gurable Open-Source Non-Volatile Memory Emulator for FPGAs -- On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs -- Design Space Exploration of Application Specific Number Formats targeting an FPGA Implementation of SPICE -- Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System -- ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures -- Applications -- FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing -- Accelerating Graph Neural Networks in Pytorch With HLS and Deep Data flows -- DNN Model Theft through Trojan Side Channel on Edge FPGA Accelerator -- Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations -- A Convolution Neural Network based Displaced Vertex Trigger for the Belle II Experiment -- On-FPGA Spiking Neural Networks for Multi-Variable End-to-End Neural Decoding -- Implementation of a Perception System for Autonomous Vehicles using a Detection-Segmentation Network in SoC FPGA -- Architectures -- Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC -- Scalable and Energy-Efficient NN Acceleration with GPU-ReRAM Architecture -- On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64 -- Evolutionary FPGA-based Spiking Neural Networks for Continual Learning -- More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding -- Energy Efficient DNN Compaction for Edge Deployment -- Special Session: Near and In-Memory Computing -- TAPRE-HBM: Trace-Based Processor Rapid Emulation using HBM on FPGAs -- An Almost Fully RRAM-based LUT Design for Reconfigurable Circuits -- A Light-weight Vision Transformer toward Near-Memory Computation on an FPGA -- PhD Forum Papers Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology -- A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography -- Simulation and Modeling for Network-on-Chip based MPSoC -- A Design-Space Exploration Framework for Application-Specification -- Machine Learning targeting Reconfigurable Computing.
001480949 506__ $$aAccess limited to authorized users.
001480949 520__ $$aThis book constitutes the proceedings of the 19th International Symposium on Applied Reconfigurable Computing, ARC 2023, which was held in Cottbus, Germany, in September 2023. The 18 full papers presented in this volume were reviewed and selected from numerous submissions. The proceedings also contain 4 short PhD papers. The contributions were organized in topical sections as follows: Design methods and tools; applications; architectures; special session: near and in-memory computing; and PhD forum papers. .
001480949 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed September 20, 2023).
001480949 650_6 $$aSystèmes adaptatifs (Informatique)$$vCongrès.
001480949 650_0 $$aAdaptive computing systems$$vCongresses.$$0(DLC)sh2002012109
001480949 655_0 $$aElectronic books.
001480949 655_7 $$aConference papers and proceedings.$$2lcgft
001480949 7001_ $$aPalumbo, Francesca,$$eeditor.
001480949 7001_ $$aKeramidas, Georgios,$$eeditor.
001480949 7001_ $$aVoros, Nikolaos S.,$$eeditor.
001480949 7001_ $$aDiniz, Pedro C.,$$eeditor.
001480949 77608 $$iPrint version: $$z3031429206$$z9783031429200$$w(OCoLC)1391129496
001480949 830_0 $$aLecture notes in computer science ;$$v14251.$$x1611-3349
001480949 852__ $$bebk
001480949 85640 $$3Springer Nature$$uhttps://univsouthin.idm.oclc.org/login?url=https://link.springer.com/10.1007/978-3-031-42921-7$$zOnline Access$$91397441.1
001480949 909CO $$ooai:library.usi.edu:1480949$$pGLOBAL_SET
001480949 980__ $$aBIB
001480949 980__ $$aEBOOK
001480949 982__ $$aEbook
001480949 983__ $$aOnline
001480949 994__ $$a92$$bISE