Advanced MOS devices and their circuit applications.

Cover
Half Title
Title Page
Copyright Page
Table of Contents
Editors
List of contributors
Preface
Acknowledgment
Chapter 1: An overview of DC/RF performance of nanosheet field effect transistor for future low-power applications
1.1 Introduction
1.2 Impact of width and thickness on device performance
1.3 Effect of substrate materials
1.4 Effect of parasitic channel height
1.5 Effect of scaling down the gate length
1.6 Temperature dependance
1.7 Impact of gate metal work function
1.8 Random dopant fluctuation

1.9 Emerging research in the field of NS-FET
1.10 Conclusion
References
Chapter 2: Device design and analysis of 3D SCwRD cylindrical (Cyl) gate-all-around (GAA) tunnel FET using split-channel and spacer engineering
2.1 Introduction
2.2 Device structure and analysis
2.3 Simulation model and parameters
2.4 Results and discussion
2.5 Conclusion
Acknowledgment
References
Chapter 3: Investigation of high-K dielectrics for single- and multi-gate FETs
3.1 Introduction
3.2 Importance of high-k materials in CMOS device scaling

3.3 Effect of high-k materials on multi-gate FETs
3.3.1 Effect of high-k materials for various temperatures
3.3.2 Effect of high-k dielectric spacer materials
3.4 Effect of dual-k spacer dielectric materials
3.5 Conclusion
References
Chapter 4: Measurement of back-gate biasing for ultra-low-power subthreshold logic in FinFET device
4.1 Introduction
4.2 FinFET technology
4.3 Results and discussion
4.4 Conclusion
References
Chapter 5: Compact analytical model for graphene field effect transistor: Drift-diffusion approach
5.1 Introduction

5.2 Electrical and mechanical properties
5.2.1 E-k relationship
5.2.2 Density of state
5.2.3 Carrier concentration
5.2.4 Channel charge
5.2.4.1 Terminal charge
5.3 Capacitance
5.3.1 Mayer technique
5.3.1.1 Gate-source capacitance Cgs
5.3.1.2 Gate-drain capacitance Cds
5.3.2 Ward-Dutton's techniques
5.3.3 Quantum capacitance
5.4 Channel potentials
5.4.1 Channel potential modeling
5.5 Drain current modeling of graphene FET: Drift-diffusion theory
5.6 Summary
Acknowledgment
References

Chapter 6: Design of CNTFET-based ternary logic flip-flop and counter circuits using unary operators
6.1 Introduction
6.2 Preliminary
6.3 Proposed design
6.3.1 Proposed unary operators
6.3.2 Proposed D-flip-flop design
6.3.3 Ternary counter design
6.4 Results and discussion
6.5 Conclusion
References
Chapter 7: Novel radiation-hardened low-power 12 transistors SRAM cell for aerospace application
7.1 Introduction
7.2 The Proposed12T cell and its operations
7.2.1 Cell structure and working operation
7.2.2 SEU recovery analysis