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Table of Contents
Intro
Preface
Acknowledgments
Author biography
Hafiz Md Hasan Babu
Outline placeholder
An overview of quantum circuits
Chapter 1 Quantum logic
1.1 Overview
1.2 Motivations towards quantum computing
1.3 The relationship between reversible and quantum logic
1.4 Quantum computers
1.5 The working principles of quantum computers
1.6 The evolution of quantum computers
1.7 Why pursue quantum computing?
1.8 Summary
Further reading
Chapter 2 Basic definitions of quantum logic
2.1 The quantum bit
2.2 The quantum gate
2.2.1 The quantum Feynman gate
2.2.2 The quantum Tofolli gate
2.2.3 The quantum Fredkin gate
2.3 Garbage outputs
2.4 Constant inputs
2.5 Area
2.6 Power
2.7 Delay
2.8 Depth
2.9 Quantum cost
2.10 Quantum gate calculation complexity
2.11 Summary
Further reading
Chapter 3 The quantum bit string comparator
3.1 Characteristics of a comparator
3.2 The magnitude comparator
3.3 The design of a quantum comparator
3.3.1 Example
3.4 Summary
Further reading
Chapter 4 The quantum adder and subtractor
4.1 The quantum adder
4.1.1 The quantum full-adder
4.2 The quantum subtractor
4.2.1 The quantum half-subtractor
4.2.2 The quantum full-subtractor
4.3 Summary
Further reading
Chapter 5 The quantum multiplexer and demultiplexer
5.1 The quantum multiplexer
5.1.1 The quantum 2-to-1 multiplexer
5.1.2 The quantum 4-to-1 multiplexer
5.1.3 The quantum 2n-to-1 multiplexer
5.2 The quantum demultiplexer
5.2.1 The quantum 1-to-2 demultiplexer
5.2.2 The quantum 1-to-4 demultiplexer
5.2.3 The quantum 1-to-2n demultiplexer
5.3 Summary
Further reading
Chapter 6 Quantum adder circuits
6.1 The carry skip adder
6.2 The quantum comparison circuit
6.3 The quantum 2-to-1 multiplier circuit.
6.4 The design of a quantum carry skip adder
6.4.1 The four-bit quantum carry skip adder
6.4.2 The n-bit quantum carry skip adder
6.4.3 Calculation of the area and power of a quantum carry skip adder circuit
6.4.4 Complexity of the n-bit quantum carry skip adder circuit
6.5 The quantum BCD adder
6.6 Summary
Further reading
Chapter 7 The quantum multiplier-accumulator
7.1 The importance of the quantum multiplier-accumulator
7.2 The multiplication technique
7.3 Reduction of the garbage outputs and ancillary inputs of quantum circuits
7.4 The design of a quantum multiplier circuit
7.4.1 The quantum ANDing circuit
7.4.2 The quantum full-adder circuit
7.4.3 The n × n-qubit quantum multiplier
7.5 Summary
Further reading
Chapter 8 The quantum divider
8.1 Division algorithms
8.1.1 Classical integer division algorithms
8.1.2 Quantum integer division algorithms
8.2 The importance of the quantum divider
8.3 The tree-based quantum division technique
8.3.1 Definitions and properties of the division technique
8.3.2 The algorithm of the division technique
8.4 The design of a quantum divider circuit
8.4.1 A technique to minimize the number of ancillary inputs in the quantum circuit realization
8.4.2 The components of the quantum divider circuit
8.5 Summary
Further reading
Chapter 9 The quantum BCD priority encoder
9.1 The properties of an encoder
9.2 The design of a quantum BCD priority encoder circuit
9.2.1 The quantum BCD priority encoder circuit
9.2.2 Analysis of the properties of the encoder circuit
9.3 Summary
Further reading
Chapter 10 The quantum decoder
10.1 The characteristics of a decoder
10.2 The design of a quantum decoder
10.2.1 The quantum decoder circuit
10.2.2 Analysis of the properties of the circuits
10.3 Summary.
Further reading
Chapter 11 The quantum square root circuit
11.1 Properties of a square root function
11.2 The design of a quantum square root circuit
11.2.1 The quantum adder/subtractor circuit
11.2.2 The quantum square root circuit
11.2.3 Analysis of the properties of the circuit
11.3 Summary
Further reading
Chapter 12 Quantum latches and counter circuits
12.1 Properties of latches
12.2 The design of the quantum latches
12.2.1 The quantum SR latch
12.2.2 The quantum D latch
12.2.3 The quantum T latch
12.2.4 The quantum J-K latch
12.3 Properties of counter circuits
12.4 The design of the quantum counters
12.4.1 The quantum asynchronous counter
12.4.2 The quantum synchronous counter
12.5 Summary
Further reading
Chapter 13 The quantum controlled ternary barrel shifter
13.1 Ternary quantum gates
13.1.1 The quantum ternary Peres gate
13.1.2 The quantum ternary modified Fredkin gate
13.2 Properties of ternary quantum circuits
13.3 The quantum barrel shifter
13.3.1 Logical right shift
13.3.2 Arithmetic right shift
13.3.3 Right rotation
13.3.4 Logical left shift
13.3.5 Arithmetic left shift
13.3.6 Left rotation
13.4 The design of a quantum ternary barrel shifter
13.4.1 The optimized quantum ternary barrel shifter
13.4.2 Properties of the designed circuit
13.5 Summary
Further reading
Chapter 14 Quantum random access memory
14.1 The quantum n-to-2n decoder
14.2 The quantum memory unit
14.3 The construction procedure of the quantum RAM
14.4 Summary
Further reading
Chapter 15 The quantum arithmetic logic unit
15.1 The design of a quantum ALU
15.1.1 The first approach
15.1.2 The second approach
15.1.3 The third approach
15.2 Summary
Further reading
Chapter 16 Applications of quantum computing technology.
16.1 Optimization
16.1.1 Roswell Park Cancer Institute
16.1.2 Volkswagen Group
16.1.3 Recruit Communications
16.2 Machine learning
16.2.1 QxBranch
16.2.2 Los Alamos National Laboratory
16.2.3 NASA
16.3 Biomedical simulations
16.4 Financial services
16.5 Computational chemistry
16.6 Logistics and scheduling
16.7 Cyber security
16.8 Circuit, software, and system fault simulation
16.9 Weather forecasting
16.10 Summary
Further reading
Outline placeholder
An overview of quantum fault-tolerant circuits
Chapter 17 Quantum fault-tolerant circuits
17.1 The need for quantum fault-tolerant circuits
17.2 The fault-tolerant quantum adder
17.2.1 The fault-tolerant full-adder
17.3 The fault-tolerant multiplier
17.3.1 The fault-tolerant signed multiplier
17.4 The quantum fault-tolerant integer divider
17.4.1 The restoring division algorithm
17.4.2 The subtractor module
17.4.3 The conditional addition operation module
17.4.4 Quantum restoring integer division circuitry
17.5 Summary
Further reading
Outline placeholder
An overview of quantum-dot cellular automata
Chapter 18 Quantum-dot cellular automata
18.1 Fundamentals of QCA circuits
Area
Delay
Kink energy
Power
Overall cost
18.2 The QCA cell
18.3 Information and data propagation
18.4 Basic QCA elements and gates
18.4.1 The QCA majority voter
18.4.2 The QCA AND gate
18.4.3 The QCA OR gate
18.4.4 The QCA NOT gate
18.4.5 The QCA wire
18.5 The QCA clock
18.5.1 Special cell arrangements and symmetric cells
18.5.2 NOT gate clock zones
18.5.3 Majority voter clock zones
18.6 Summary
Further reading
Chapter 19 QCA adder and subtractor
19.1 The Ex-OR gate
19.2 The QCA half-adder and half-subtractor
19.3 The QCA full-adder and full-subtractor.
19.3.1 Implementation of the full-adder and full-subtractor
19.4 Summary
Further reading
Chapter 20 The QCA multiplier and divider
20.1 The QCA multiplier
20.1.1 Multiplication networks
20.1.2 QCA multiplication networks
20.1.3 Multiplier design
20.1.4 QCA implementation
20.2 The QCA divider
20.2.1 The non-restoring binary divider
20.2.2 Divider implementation
20.3 Summary
Further reading
Chapter 21 QCA asynchronous and synchronous counters
21.1 The asynchronous counter
21.1.1 The dual-edge triggered J-K flip-flop
21.1.2 The design of dual-edge triggered J-K flip-flop
21.1.3 The asynchronous backward counter
21.2 The synchronous counter
21.2.1 QCA synchronous counters
21.3 Summary
Further reading
Chapter 22 The QCA decoder and encoder
22.1 The QCA decoder
22.1.1 The QCA 2-to-4 decoder
A. Calculation for AB̄ ̄
B. Calculation for AB
22.1.2 The QCA 3-to-8 decoder
22.2 The QCA encoder
22.2.1 The QCA turbo encoder design
22.2.2 The RC encoder with single-feedback
22.2.3 The RC encoder with multi-feedback
22.3 Summary
Further reading
Chapter 23 The QCA multiplexer and demultiplexer
23.1 The QCA 2-to-1 multiplexer
23.2 The QCA 4-to-1 multiplexer
23.3 The QCA 1-to-2 demultiplexer
23.4 The QCA 1-to-4 demultiplexer
23.5 Multiplexing/demultiplexing using QCA
23.5.1 The effect of the selector line (S0,S1) on the 2-to-1 MUX/1-to-2 DEMUX
23.6 Summary
Further reading
Chapter 24 The QCA RAM, ROM, and processor
24.1 The RAM cell
24.2 The QCA ROM
24.3 The QCA processor
24.3.1 Instruction memory
24.3.2 Data memory
24.3.3 The arithmetic logic unit
24.3.4 The integrated processor
24.4 Summary
Further reading.
Preface
Acknowledgments
Author biography
Hafiz Md Hasan Babu
Outline placeholder
An overview of quantum circuits
Chapter 1 Quantum logic
1.1 Overview
1.2 Motivations towards quantum computing
1.3 The relationship between reversible and quantum logic
1.4 Quantum computers
1.5 The working principles of quantum computers
1.6 The evolution of quantum computers
1.7 Why pursue quantum computing?
1.8 Summary
Further reading
Chapter 2 Basic definitions of quantum logic
2.1 The quantum bit
2.2 The quantum gate
2.2.1 The quantum Feynman gate
2.2.2 The quantum Tofolli gate
2.2.3 The quantum Fredkin gate
2.3 Garbage outputs
2.4 Constant inputs
2.5 Area
2.6 Power
2.7 Delay
2.8 Depth
2.9 Quantum cost
2.10 Quantum gate calculation complexity
2.11 Summary
Further reading
Chapter 3 The quantum bit string comparator
3.1 Characteristics of a comparator
3.2 The magnitude comparator
3.3 The design of a quantum comparator
3.3.1 Example
3.4 Summary
Further reading
Chapter 4 The quantum adder and subtractor
4.1 The quantum adder
4.1.1 The quantum full-adder
4.2 The quantum subtractor
4.2.1 The quantum half-subtractor
4.2.2 The quantum full-subtractor
4.3 Summary
Further reading
Chapter 5 The quantum multiplexer and demultiplexer
5.1 The quantum multiplexer
5.1.1 The quantum 2-to-1 multiplexer
5.1.2 The quantum 4-to-1 multiplexer
5.1.3 The quantum 2n-to-1 multiplexer
5.2 The quantum demultiplexer
5.2.1 The quantum 1-to-2 demultiplexer
5.2.2 The quantum 1-to-4 demultiplexer
5.2.3 The quantum 1-to-2n demultiplexer
5.3 Summary
Further reading
Chapter 6 Quantum adder circuits
6.1 The carry skip adder
6.2 The quantum comparison circuit
6.3 The quantum 2-to-1 multiplier circuit.
6.4 The design of a quantum carry skip adder
6.4.1 The four-bit quantum carry skip adder
6.4.2 The n-bit quantum carry skip adder
6.4.3 Calculation of the area and power of a quantum carry skip adder circuit
6.4.4 Complexity of the n-bit quantum carry skip adder circuit
6.5 The quantum BCD adder
6.6 Summary
Further reading
Chapter 7 The quantum multiplier-accumulator
7.1 The importance of the quantum multiplier-accumulator
7.2 The multiplication technique
7.3 Reduction of the garbage outputs and ancillary inputs of quantum circuits
7.4 The design of a quantum multiplier circuit
7.4.1 The quantum ANDing circuit
7.4.2 The quantum full-adder circuit
7.4.3 The n × n-qubit quantum multiplier
7.5 Summary
Further reading
Chapter 8 The quantum divider
8.1 Division algorithms
8.1.1 Classical integer division algorithms
8.1.2 Quantum integer division algorithms
8.2 The importance of the quantum divider
8.3 The tree-based quantum division technique
8.3.1 Definitions and properties of the division technique
8.3.2 The algorithm of the division technique
8.4 The design of a quantum divider circuit
8.4.1 A technique to minimize the number of ancillary inputs in the quantum circuit realization
8.4.2 The components of the quantum divider circuit
8.5 Summary
Further reading
Chapter 9 The quantum BCD priority encoder
9.1 The properties of an encoder
9.2 The design of a quantum BCD priority encoder circuit
9.2.1 The quantum BCD priority encoder circuit
9.2.2 Analysis of the properties of the encoder circuit
9.3 Summary
Further reading
Chapter 10 The quantum decoder
10.1 The characteristics of a decoder
10.2 The design of a quantum decoder
10.2.1 The quantum decoder circuit
10.2.2 Analysis of the properties of the circuits
10.3 Summary.
Further reading
Chapter 11 The quantum square root circuit
11.1 Properties of a square root function
11.2 The design of a quantum square root circuit
11.2.1 The quantum adder/subtractor circuit
11.2.2 The quantum square root circuit
11.2.3 Analysis of the properties of the circuit
11.3 Summary
Further reading
Chapter 12 Quantum latches and counter circuits
12.1 Properties of latches
12.2 The design of the quantum latches
12.2.1 The quantum SR latch
12.2.2 The quantum D latch
12.2.3 The quantum T latch
12.2.4 The quantum J-K latch
12.3 Properties of counter circuits
12.4 The design of the quantum counters
12.4.1 The quantum asynchronous counter
12.4.2 The quantum synchronous counter
12.5 Summary
Further reading
Chapter 13 The quantum controlled ternary barrel shifter
13.1 Ternary quantum gates
13.1.1 The quantum ternary Peres gate
13.1.2 The quantum ternary modified Fredkin gate
13.2 Properties of ternary quantum circuits
13.3 The quantum barrel shifter
13.3.1 Logical right shift
13.3.2 Arithmetic right shift
13.3.3 Right rotation
13.3.4 Logical left shift
13.3.5 Arithmetic left shift
13.3.6 Left rotation
13.4 The design of a quantum ternary barrel shifter
13.4.1 The optimized quantum ternary barrel shifter
13.4.2 Properties of the designed circuit
13.5 Summary
Further reading
Chapter 14 Quantum random access memory
14.1 The quantum n-to-2n decoder
14.2 The quantum memory unit
14.3 The construction procedure of the quantum RAM
14.4 Summary
Further reading
Chapter 15 The quantum arithmetic logic unit
15.1 The design of a quantum ALU
15.1.1 The first approach
15.1.2 The second approach
15.1.3 The third approach
15.2 Summary
Further reading
Chapter 16 Applications of quantum computing technology.
16.1 Optimization
16.1.1 Roswell Park Cancer Institute
16.1.2 Volkswagen Group
16.1.3 Recruit Communications
16.2 Machine learning
16.2.1 QxBranch
16.2.2 Los Alamos National Laboratory
16.2.3 NASA
16.3 Biomedical simulations
16.4 Financial services
16.5 Computational chemistry
16.6 Logistics and scheduling
16.7 Cyber security
16.8 Circuit, software, and system fault simulation
16.9 Weather forecasting
16.10 Summary
Further reading
Outline placeholder
An overview of quantum fault-tolerant circuits
Chapter 17 Quantum fault-tolerant circuits
17.1 The need for quantum fault-tolerant circuits
17.2 The fault-tolerant quantum adder
17.2.1 The fault-tolerant full-adder
17.3 The fault-tolerant multiplier
17.3.1 The fault-tolerant signed multiplier
17.4 The quantum fault-tolerant integer divider
17.4.1 The restoring division algorithm
17.4.2 The subtractor module
17.4.3 The conditional addition operation module
17.4.4 Quantum restoring integer division circuitry
17.5 Summary
Further reading
Outline placeholder
An overview of quantum-dot cellular automata
Chapter 18 Quantum-dot cellular automata
18.1 Fundamentals of QCA circuits
Area
Delay
Kink energy
Power
Overall cost
18.2 The QCA cell
18.3 Information and data propagation
18.4 Basic QCA elements and gates
18.4.1 The QCA majority voter
18.4.2 The QCA AND gate
18.4.3 The QCA OR gate
18.4.4 The QCA NOT gate
18.4.5 The QCA wire
18.5 The QCA clock
18.5.1 Special cell arrangements and symmetric cells
18.5.2 NOT gate clock zones
18.5.3 Majority voter clock zones
18.6 Summary
Further reading
Chapter 19 QCA adder and subtractor
19.1 The Ex-OR gate
19.2 The QCA half-adder and half-subtractor
19.3 The QCA full-adder and full-subtractor.
19.3.1 Implementation of the full-adder and full-subtractor
19.4 Summary
Further reading
Chapter 20 The QCA multiplier and divider
20.1 The QCA multiplier
20.1.1 Multiplication networks
20.1.2 QCA multiplication networks
20.1.3 Multiplier design
20.1.4 QCA implementation
20.2 The QCA divider
20.2.1 The non-restoring binary divider
20.2.2 Divider implementation
20.3 Summary
Further reading
Chapter 21 QCA asynchronous and synchronous counters
21.1 The asynchronous counter
21.1.1 The dual-edge triggered J-K flip-flop
21.1.2 The design of dual-edge triggered J-K flip-flop
21.1.3 The asynchronous backward counter
21.2 The synchronous counter
21.2.1 QCA synchronous counters
21.3 Summary
Further reading
Chapter 22 The QCA decoder and encoder
22.1 The QCA decoder
22.1.1 The QCA 2-to-4 decoder
A. Calculation for AB̄ ̄
B. Calculation for AB
22.1.2 The QCA 3-to-8 decoder
22.2 The QCA encoder
22.2.1 The QCA turbo encoder design
22.2.2 The RC encoder with single-feedback
22.2.3 The RC encoder with multi-feedback
22.3 Summary
Further reading
Chapter 23 The QCA multiplexer and demultiplexer
23.1 The QCA 2-to-1 multiplexer
23.2 The QCA 4-to-1 multiplexer
23.3 The QCA 1-to-2 demultiplexer
23.4 The QCA 1-to-4 demultiplexer
23.5 Multiplexing/demultiplexing using QCA
23.5.1 The effect of the selector line (S0,S1) on the 2-to-1 MUX/1-to-2 DEMUX
23.6 Summary
Further reading
Chapter 24 The QCA RAM, ROM, and processor
24.1 The RAM cell
24.2 The QCA ROM
24.3 The QCA processor
24.3.1 Instruction memory
24.3.2 Data memory
24.3.3 The arithmetic logic unit
24.3.4 The integrated processor
24.4 Summary
Further reading.