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Cover
Title
Copyright
End User License Agreement
Contents
Preface
Acknowledgements
List of Contributors
Role of Nanomaterials: In Novel Semiconductor Field Effect Transistors
Chandra Keerthi Pothina1, J. Lakshmi Prasanna1, M. Ravi Kumar1 and Chella Santhosh1,*
INTRODUCTION
ROLE OF 2D NANOMATERIALS OR NANOSHEETS IN SEMICONDUCTOR FETS
Single Layer MoS2 Field Effect Transistors
Two-Dimensional Indium-Selenide Field-Effect Transistors
ROLE OF ONE-DIMENSIONAL NANOMATERIALS IN SEMICONDUCTOR FETS
Nanowires and Their Role in Field Effect Transistors
Gate All Around and Multi-Bridge Channel Field Effect Transistors
Carbon Nanotubes and Carbon Nanotube Field Effect Transistors
Back Gated CNTFET
Top Gated CNTFET
Wrap Around or Gate All Around CNTFET
Suspended CNTFETs
ROLE OF ZERO DIMENSIONAL NANOMATERIALS IN SEMICONDUCTOR FETS
Quantum Dots
Working of Quantum Dots
Quantum Dots in Field Effect Transistors
Light Emitting Field Effect Transistor
Quantum Dot Gate Field Effect Transistor
Analysis of Thermal Transport in a Nanoscale Transistor Using Lattice Boltzmann Method
Boundary Condition
CONCLUSION
REFERENCES
Transition from Conventional FETs to Novel FETs, SOI, Double Gate, Triple Gate, and GAA FETS
Jyoti Kandpal1,* and Ekta Goel2
INTRODUCTION
History of I.C.
Moore's First Law
Moore's Second Law
Moore's Law in the Future
Moore's Law's Applications
TYPE OF PLANAR TECHNOLOGY
Complementary Metal Oxide Semiconductor (CMOS)
Structure for SOI-Based MOSFETs
Double Gate (D.G.) MOSFET Technology
Fin Field Effect Transistor (FinFET)
NANO TRANSISTOR
NANOWIRE (NW) TRANSISTORS
CNTFET
GRAPHENE NANORIBBON (GNR) TRANSISTOR
SINGLE-ELECTRON TRANSISTORS (SETS)
QUANTUM-DOT CELLULAR AUTOMATA (QCA)
TRI-GATE STRUCTURE
PI GATE.
GATE ALL AROUND (GAA) FET
OMEGA FET
Applications of Field Effect Transistor (FET)
CHALLENGES
CONCLUSION
ACKNOWLEDGEMENT
REFERENCES
FinFETs and their Applications
Savitesh Madhulika Sharma1,* and Avtar Singh2
INTRODUCTION
CLASSIFICATION OF THE FINFETS
Based on Number of Gates
Based on Number of Terminals
Tied Gate (TG) FinFET
Independent Gate (IG) FinFET
Based on Bulk Oxide
Bulk FinFET
SOI FinFET
Based on Symmetricity
Symmetric FinFET
Asymmetric FinFET
DEVICE PHYSICS
FABRICATION OF FINFETS
FINFET MODELING
CHARACTERIZATION OF FINFET
DESIGN CHALLENGES AND RELIABILITY ISSUES
FinFET's Shape of Fin
Doping Concentration
Integration of the FinFETs
Parasitic Capacitances
Orientation of Fins
Reliability of FinFETs
Variability of Fin Dimensions
Strain Engineering
PERFORMANCE IMPROVEMENT ENGINEERING TECHNIQUES
Structural Variations
Body Thickness
Oxide Thickness
Implant Energy
Gate Stack
CIRCUIT APPLICATIONS
Inverter
SRAM
Flash Memory
Reference Voltage Circuit
CONCLUDING REMARKS
REFERENCES
Supply Voltage Scaling for Energy Efficient FinFET Logic
Sarita Yadav1,*, Nitanshu Chauhan1, Shobhit Tyagi2, Arvind Sharma3, Shashank Banchhor4, Rajiv Joshi5, Rajendra Pratap6 and Bulusu Anand4
INTRODUCTION
Supply Voltage Scaling
Voltage Scaling in Nanoscale Devices
EXPERIMENTAL SETUP
MINIMUM SUPPLY VOLTAGE MODEL
Development of Mathematical I-V Relationship for Sub-100mV Biases for FinFETs
Dependence of Temperature on Empirical Parameters
Estimation of Limit on VDD for Inverter
Derivation of Limit of Minimum Supply Voltage for NAND Gate
CONCLUSION
REFERENCES
Graphene FET for Microwave and Terahertz Applications
Neetu Joshi1,*
NATURE OF WORK
INTRODUCTION
PROPERTIES OF GRAPHENE.
Optical Properties
Electronic Properties
Terahertz Properties of Graphene
Plasmonics
Surface Plasmons
GRAPHENE FIELD-EFFECT TRANSISTORS
DESIGN AND MODELING
CHARACTERIZATION AND FABRICATION DEVELOPMENTS AND CHALLENGES
Characterization
Fabrication
Electron Beam Lithography
Source and Drain Metal Contacts
High-k Material Deposition by ALD Method
Gate Electrode
APPLICATIONS IN BIOSENSING AND HIGH FREQUENCIES
Mixers
Modeling
Drift Diffusion Carrier Transport
CONCLUSION AND FUTURE SCOPE
REFERENCES
Analysis of Negative to Positive Differential Conductance Transition in NCFET and Guidelines for Analog Circuit Designing
Nitanshu Chauhan1,*, Sudeb Dasgupta2 and Anand Bulusu2
INTRODUCTION
NCFET ARCHITECTURES
Metal-Ferro-Metal-Insulator-Semiconductor (MFMIS) FET
Metal-Ferro-Insulator-Semiconductor (MFIS) FET
VOLTAGE AMPLIFICATION AND SUB-THRESHOLD SWING OF NCFET
DEVICE STRUCTURE AND TCAD MODELS CALIBRATION
NEGATIVE TO POSITIVE DIFFERENTIAL CONDUCTANCE TRANSITION IN NC FDSOI
Physical Insight of NDC to PDC Transition
Impact of Back Bias on NDC to PDC Transition
Impact of Interface Trap Charge on NDC to PDC Transition
CIRCUIT DESIGNING USING NDC TO PDC TRANSITION
Designing of Single Stage Common Source Amplifier
Current Mirror Realization
Impact of Gate Length Variation on Amplifier Gain
CONCLUSION
REFERENCES
CMOS Compatible Single-Gate Single Electron Transistor (SG-SET) Based Hybrid SETMOS Logic
Raj Shah1,* and Rasika Dhavse1
INTRODUCTION
SG-SET DESIGN AND SIMULATION
Novel Hybrid SETMOS Technique
RESULTS AND DISCUSSION
Thermal analysis of the Proposed Hybrid SETMOS
CONCLUDING REMARKS
ACKNOWLEDGEMENTS
REFERENCES
Extensive Investigation on Even-Transistor- Configuration CMOS-based SRAM.
Dharmendra Singh Yadav1,*, Prabhat Singh1, Vibhash Choudhary1 and Rakesh Murthy Gangadari1
INTRODUCTION
VARIOUS TOPOLOGIES OF SRAM AND ITS OPERATION
6T SRAM and its Operation
Hold Mode
Read Mode
Write Mode
8T SRAM and its Operation
Hold Mode
Read Mode
Write Mode
10T SRAM and its Operation
12T SRAM and its Operation
READ DELAY CALCULATION AND ITS COMPARISON
WRITE DELAY CALCULATION AND ITS COMPARISON
AVERAGE POWER DISSIPATION
ANALYSIS OF STATIC NOISE MARGIN
Hold Static Noise Margin (SNMH)
Read Static Noise Margin (SNMR)
Write Static Noise Margin (SNMW)
CONCLUSION
REFERENCES
A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI
J. Sravana1,*, A. Karthik2 and T. Dinesh3
INTRODUCTION
BRIEF ON LEAKAGE CURRENT COMPONENT
Sources of Leakage Currents
SURVEY ON LEVELS TO REDUCE LEAKAGE POWER
Multiple Threshold Complementary MOS
Variable Threshold Metal Oxide Semiconductor
Input Vector Control
Lector
Galeor
Onofic (ON/OFF IC)
COMPARISON OF LEAKAGE MINIMIZATION TECHNIQUE
ONOFIC POWER OPTIMIZATION TECHNIQUE FOR DOMINOS CIRCUITS
Foot Driven Stack Transistor Domino Logic (FDSTDL)
1-BIT ADIABATIC ADDER CIRCUIT USING ECRL TECHNIQUE
RESULTS
CONCLUSION
FUTURE SCOPE
REFERENCES
Subject Index
Back Cover.
Title
Copyright
End User License Agreement
Contents
Preface
Acknowledgements
List of Contributors
Role of Nanomaterials: In Novel Semiconductor Field Effect Transistors
Chandra Keerthi Pothina1, J. Lakshmi Prasanna1, M. Ravi Kumar1 and Chella Santhosh1,*
INTRODUCTION
ROLE OF 2D NANOMATERIALS OR NANOSHEETS IN SEMICONDUCTOR FETS
Single Layer MoS2 Field Effect Transistors
Two-Dimensional Indium-Selenide Field-Effect Transistors
ROLE OF ONE-DIMENSIONAL NANOMATERIALS IN SEMICONDUCTOR FETS
Nanowires and Their Role in Field Effect Transistors
Gate All Around and Multi-Bridge Channel Field Effect Transistors
Carbon Nanotubes and Carbon Nanotube Field Effect Transistors
Back Gated CNTFET
Top Gated CNTFET
Wrap Around or Gate All Around CNTFET
Suspended CNTFETs
ROLE OF ZERO DIMENSIONAL NANOMATERIALS IN SEMICONDUCTOR FETS
Quantum Dots
Working of Quantum Dots
Quantum Dots in Field Effect Transistors
Light Emitting Field Effect Transistor
Quantum Dot Gate Field Effect Transistor
Analysis of Thermal Transport in a Nanoscale Transistor Using Lattice Boltzmann Method
Boundary Condition
CONCLUSION
REFERENCES
Transition from Conventional FETs to Novel FETs, SOI, Double Gate, Triple Gate, and GAA FETS
Jyoti Kandpal1,* and Ekta Goel2
INTRODUCTION
History of I.C.
Moore's First Law
Moore's Second Law
Moore's Law in the Future
Moore's Law's Applications
TYPE OF PLANAR TECHNOLOGY
Complementary Metal Oxide Semiconductor (CMOS)
Structure for SOI-Based MOSFETs
Double Gate (D.G.) MOSFET Technology
Fin Field Effect Transistor (FinFET)
NANO TRANSISTOR
NANOWIRE (NW) TRANSISTORS
CNTFET
GRAPHENE NANORIBBON (GNR) TRANSISTOR
SINGLE-ELECTRON TRANSISTORS (SETS)
QUANTUM-DOT CELLULAR AUTOMATA (QCA)
TRI-GATE STRUCTURE
PI GATE.
GATE ALL AROUND (GAA) FET
OMEGA FET
Applications of Field Effect Transistor (FET)
CHALLENGES
CONCLUSION
ACKNOWLEDGEMENT
REFERENCES
FinFETs and their Applications
Savitesh Madhulika Sharma1,* and Avtar Singh2
INTRODUCTION
CLASSIFICATION OF THE FINFETS
Based on Number of Gates
Based on Number of Terminals
Tied Gate (TG) FinFET
Independent Gate (IG) FinFET
Based on Bulk Oxide
Bulk FinFET
SOI FinFET
Based on Symmetricity
Symmetric FinFET
Asymmetric FinFET
DEVICE PHYSICS
FABRICATION OF FINFETS
FINFET MODELING
CHARACTERIZATION OF FINFET
DESIGN CHALLENGES AND RELIABILITY ISSUES
FinFET's Shape of Fin
Doping Concentration
Integration of the FinFETs
Parasitic Capacitances
Orientation of Fins
Reliability of FinFETs
Variability of Fin Dimensions
Strain Engineering
PERFORMANCE IMPROVEMENT ENGINEERING TECHNIQUES
Structural Variations
Body Thickness
Oxide Thickness
Implant Energy
Gate Stack
CIRCUIT APPLICATIONS
Inverter
SRAM
Flash Memory
Reference Voltage Circuit
CONCLUDING REMARKS
REFERENCES
Supply Voltage Scaling for Energy Efficient FinFET Logic
Sarita Yadav1,*, Nitanshu Chauhan1, Shobhit Tyagi2, Arvind Sharma3, Shashank Banchhor4, Rajiv Joshi5, Rajendra Pratap6 and Bulusu Anand4
INTRODUCTION
Supply Voltage Scaling
Voltage Scaling in Nanoscale Devices
EXPERIMENTAL SETUP
MINIMUM SUPPLY VOLTAGE MODEL
Development of Mathematical I-V Relationship for Sub-100mV Biases for FinFETs
Dependence of Temperature on Empirical Parameters
Estimation of Limit on VDD for Inverter
Derivation of Limit of Minimum Supply Voltage for NAND Gate
CONCLUSION
REFERENCES
Graphene FET for Microwave and Terahertz Applications
Neetu Joshi1,*
NATURE OF WORK
INTRODUCTION
PROPERTIES OF GRAPHENE.
Optical Properties
Electronic Properties
Terahertz Properties of Graphene
Plasmonics
Surface Plasmons
GRAPHENE FIELD-EFFECT TRANSISTORS
DESIGN AND MODELING
CHARACTERIZATION AND FABRICATION DEVELOPMENTS AND CHALLENGES
Characterization
Fabrication
Electron Beam Lithography
Source and Drain Metal Contacts
High-k Material Deposition by ALD Method
Gate Electrode
APPLICATIONS IN BIOSENSING AND HIGH FREQUENCIES
Mixers
Modeling
Drift Diffusion Carrier Transport
CONCLUSION AND FUTURE SCOPE
REFERENCES
Analysis of Negative to Positive Differential Conductance Transition in NCFET and Guidelines for Analog Circuit Designing
Nitanshu Chauhan1,*, Sudeb Dasgupta2 and Anand Bulusu2
INTRODUCTION
NCFET ARCHITECTURES
Metal-Ferro-Metal-Insulator-Semiconductor (MFMIS) FET
Metal-Ferro-Insulator-Semiconductor (MFIS) FET
VOLTAGE AMPLIFICATION AND SUB-THRESHOLD SWING OF NCFET
DEVICE STRUCTURE AND TCAD MODELS CALIBRATION
NEGATIVE TO POSITIVE DIFFERENTIAL CONDUCTANCE TRANSITION IN NC FDSOI
Physical Insight of NDC to PDC Transition
Impact of Back Bias on NDC to PDC Transition
Impact of Interface Trap Charge on NDC to PDC Transition
CIRCUIT DESIGNING USING NDC TO PDC TRANSITION
Designing of Single Stage Common Source Amplifier
Current Mirror Realization
Impact of Gate Length Variation on Amplifier Gain
CONCLUSION
REFERENCES
CMOS Compatible Single-Gate Single Electron Transistor (SG-SET) Based Hybrid SETMOS Logic
Raj Shah1,* and Rasika Dhavse1
INTRODUCTION
SG-SET DESIGN AND SIMULATION
Novel Hybrid SETMOS Technique
RESULTS AND DISCUSSION
Thermal analysis of the Proposed Hybrid SETMOS
CONCLUDING REMARKS
ACKNOWLEDGEMENTS
REFERENCES
Extensive Investigation on Even-Transistor- Configuration CMOS-based SRAM.
Dharmendra Singh Yadav1,*, Prabhat Singh1, Vibhash Choudhary1 and Rakesh Murthy Gangadari1
INTRODUCTION
VARIOUS TOPOLOGIES OF SRAM AND ITS OPERATION
6T SRAM and its Operation
Hold Mode
Read Mode
Write Mode
8T SRAM and its Operation
Hold Mode
Read Mode
Write Mode
10T SRAM and its Operation
12T SRAM and its Operation
READ DELAY CALCULATION AND ITS COMPARISON
WRITE DELAY CALCULATION AND ITS COMPARISON
AVERAGE POWER DISSIPATION
ANALYSIS OF STATIC NOISE MARGIN
Hold Static Noise Margin (SNMH)
Read Static Noise Margin (SNMR)
Write Static Noise Margin (SNMW)
CONCLUSION
REFERENCES
A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI
J. Sravana1,*, A. Karthik2 and T. Dinesh3
INTRODUCTION
BRIEF ON LEAKAGE CURRENT COMPONENT
Sources of Leakage Currents
SURVEY ON LEVELS TO REDUCE LEAKAGE POWER
Multiple Threshold Complementary MOS
Variable Threshold Metal Oxide Semiconductor
Input Vector Control
Lector
Galeor
Onofic (ON/OFF IC)
COMPARISON OF LEAKAGE MINIMIZATION TECHNIQUE
ONOFIC POWER OPTIMIZATION TECHNIQUE FOR DOMINOS CIRCUITS
Foot Driven Stack Transistor Domino Logic (FDSTDL)
1-BIT ADIABATIC ADDER CIRCUIT USING ECRL TECHNIQUE
RESULTS
CONCLUSION
FUTURE SCOPE
REFERENCES
Subject Index
Back Cover.