@article{695209,
      note = {Includes index.},
      author = {Mehta, Ashok B.,},
      url = {http://library.usi.edu/record/695209},
      title = {SystemVerilog assertions and functional coverage guide to  language, methodology and applications / [electronic  resource] :},
      abstract = {This book provides a hands-on, application-oriented guide  to the language and methodology of both SystemVerilog  Assertions and SytemVerilog Functional Coverage. Readers  will benefit from the step-by-step approach to functional  hardware verification, which will enable them to uncover  hidden and hard to find bugs, point directly to the source  of the bug, provide for a clean and easy way to model  complex timing checks and objectively answer the question  'have we functionally verified everything'. Written by a  professional end-user of both SystemVerilog Assertions and  SystemVerilog Functional Coverage, this book explains each  concept with easy to understand examples, simulation logs  and applications derived from real projects.},
      doi = {https://doi.org/10.1007/978-1-4614-7324-4},
      recid = {695209},
      pages = {1 online resource (xxxiii, 356 pages) :},
}