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000695209 020__ $$a9781461473244 $$qelectronic book
000695209 020__ $$a1461473241 $$qelectronic book
000695209 020__ $$z9781461473237
000695209 0247_ $$a10.1007/978-1-4614-7324-4$$2doi
000695209 035__ $$aSP(OCoLC)ocn856650228
000695209 035__ $$aSP(OCoLC)856650228
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000695209 049__ $$aISEA
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000695209 08204 $$a621.39/2$$223
000695209 1001_ $$aMehta, Ashok B.,$$eauthor.
000695209 24510 $$aSystemVerilog assertions and functional coverage$$h[electronic resource] :$$bguide to language, methodology and applications /$$cAshok B. Mehta.
000695209 264_1 $$aNew York, NY :$$bSpringer,$$c[2013]
000695209 264_4 $$c©2014
000695209 300__ $$a1 online resource (xxxiii, 356 pages) :$$billustrations
000695209 336__ $$atext$$btxt$$2rdacontent
000695209 337__ $$acomputer$$bc$$2rdamedia
000695209 338__ $$aonline resource$$bcr$$2rdacarrier
000695209 500__ $$aIncludes index.
000695209 5050_ $$aIntroduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- expect -- assume and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800 2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material).
000695209 506__ $$aAccess limited to authorized users.
000695209 520__ $$aThis book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.
000695209 588__ $$aDescription based on online resource; title from PDF title page (SpringerLink, viewed August 20, 2013).
000695209 650_0 $$aVerilog (Computer hardware description language)
000695209 650_0 $$aElectronic digital computers$$xDesign and construction.
000695209 650_0 $$aIntegrated circuits$$xVerification.
000695209 85280 $$bebk$$hSpringerLink
000695209 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://dx.doi.org/10.1007/978-1-4614-7324-4$$zOnline Access
000695209 909CO $$ooai:library.usi.edu:695209$$pGLOBAL_SET
000695209 980__ $$aEBOOK
000695209 980__ $$aBIB
000695209 982__ $$aEbook
000695209 983__ $$aOnline
000695209 994__ $$a92$$bISE