000695556 000__ 03799cam\a2200481Ki\4500
000695556 001__ 695556
000695556 005__ 20230306135445.0
000695556 006__ m\\\\\o\\d\\\\\\\\
000695556 007__ cr\cnu|||unuuu
000695556 008__ 131009s2014\\\\gw\a\\\\ob\\\\100\0\eng\d
000695556 0167_ $$a016641931$$2Uk
000695556 020__ $$a9783319014180 $$qelectronic book
000695556 020__ $$a3319014188 $$qelectronic book
000695556 020__ $$z9783319014173
000695556 0247_ $$a10.1007/978-3-319-01418-0$$2doi
000695556 035__ $$aSP(OCoLC)ocn859673015
000695556 035__ $$aSP(OCoLC)859673015
000695556 040__ $$aGW5XE$$beng$$erda$$epn$$cGW5XE$$dN$T$$dYDXCP$$dCOO$$dUKMGB$$dGGVRL
000695556 049__ $$aISEA
000695556 050_4 $$aTK7895.E42
000695556 08204 $$a006.2/2$$223
000695556 1112_ $$aFDL (Conference)$$d(2012 :$$cVienna University of Technology)
000695556 24510 $$aModels, methods, and tools for complex chip design$$h[electronic resource] :$$bselected contributions from FDL 2012 /$$cJan Haase, editor.
000695556 264_1 $$aCham :$$bSpringer,$$c[2013?]
000695556 264_4 $$c©2014
000695556 300__ $$a1 online resource (xv, 221 pages) :$$billustrations (some color).
000695556 336__ $$atext$$btxt$$2rdacontent
000695556 337__ $$acomputer$$bc$$2rdamedia
000695556 338__ $$aonline resource$$bcr$$2rdacarrier
000695556 4901_ $$aLecture notes in electrical engineering,$$x1876-1100 ;$$vv.265
000695556 504__ $$aIncludes bibliographical references.
000695556 5050_ $$aFormal Plausibility Checks for Environment -- Efficient Refinement Strategy Exploiting Component Properties in A CEGAR Process -- Formal Specification Level -- Power Estimation Methodology for SystemC -- SystemC Analysis for Nondeterminism Anomalies -- A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS -- Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs -- Model Based Design of Distributed Embedded Cyber Physical Systems -- Model-driven Methodology for the Development of Multi-level Executable Environments -- The Concept and Study of Grid Responsiveness -- Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components -- Methodology and Example-Driven Interconnect Synthesis for Designing Heterogenous Coarse-Grain Reconfigurable Architectures.
000695556 506__ $$aAccess limited to authorized users.
000695556 520__ $$aThis book brings together a selection of the best papers from the fifteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2012 at Vienna University of Technology, Vienna, Austria. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. Covers Assertion Based Design, Verification & Debug; Includes language-based modeling and design techniques for embedded systems; Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains; Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE).
000695556 588__ $$aDescription based on online resource; title from PDF title page (SpringerLink, viewed September 24, 2013).
000695556 650_0 $$aEmbedded computer systems$$xDesign and construction$$vCongresses.
000695556 650_0 $$aIntegrated circuits$$xDesign and construction$$vCongresses.
000695556 7001_ $$aHaase, Jan,$$eeditor of compilation.
000695556 830_0 $$aLecture notes in electrical engineering ;$$v265.$$x1876-1100
000695556 85280 $$bebk$$hSpringerLink
000695556 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://dx.doi.org/10.1007/978-3-319-01418-0$$zOnline Access
000695556 909CO $$ooai:library.usi.edu:695556$$pGLOBAL_SET
000695556 980__ $$aEBOOK
000695556 980__ $$aBIB
000695556 982__ $$aEbook
000695556 983__ $$aOnline
000695556 994__ $$a92$$bISE