@article{695686,
      author = {Neuberger, Gustavo, and Wirth, Gilson, and Reis, Ricardo  A. L.},
      url = {http://library.usi.edu/record/695686},
      title = {Protecting chips against hold time violations due to  variability [electronic resource]  /},
      abstract = {This book presents physical understanding, modeling and  simulation, on-chip characterization, layout solutions, and  design techniques that are effective to enhance the  reliability of various circuit units. The consequences of  variability to several aspects of circuit design, such as  logic gates, storage elements, clock distribution, and any  other that can be affected by process variations are  discussed, with a key focus on storage elements. The  authors present a statistical analysis of the critical  clock skew in several test paths, due to process  variability in 130nm and 90nm CMOS technology. To  facilitate an on-wafer test, a measurement circuit with a  precision compatible to the speed of the technology is  described.},
      doi = {https://doi.org/10.1007/978-94-007-2427-3},
      recid = {695686},
      pages = {1 online resource (xi, 107 pages) :},
}