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000695686 020__ $$a9789400724273 $$qelectronic book
000695686 020__ $$a9400724276 $$qelectronic book
000695686 020__ $$z9789400724266
000695686 0247_ $$a10.1007/978-94-007-2427-3$$2doi
000695686 035__ $$aSP(OCoLC)ocn861217159
000695686 035__ $$aSP(OCoLC)861217159
000695686 040__ $$aGW5XE$$beng$$erda$$epn$$cGW5XE$$dN$T$$dYDXCP$$dCOO
000695686 049__ $$aISEA
000695686 050_4 $$aTK7874.65
000695686 08204 $$a621.3815$$223
000695686 1001_ $$aNeuberger, Gustavo,$$eauthor.
000695686 24510 $$aProtecting chips against hold time violations due to variability$$h[electronic resource]  /$$cGustavo Neuberger, Gilson Wirth, Ricardo Reis.
000695686 264_1 $$aNew York :$$bSpringer,$$c[2013?]
000695686 264_4 $$c©2014
000695686 300__ $$a1 online resource (xi, 107 pages) :$$billustrations (some color)
000695686 336__ $$atext$$btxt$$2rdacontent
000695686 337__ $$acomputer$$bc$$2rdamedia
000695686 338__ $$aonline resource$$bcr$$2rdacarrier
000695686 504__ $$aIncludes bibliographical references.
000695686 5050_ $$aIntroduction, Process Variations and Flip-Flops -- Process Variability -- Flip-Flops and Hold Time Violations -- Circuits Under Test -- Measurement Circuits -- Experimental Results -- Systematic and Random Variablility -- Normality Tests -- Probability of Hold Time Violations -- Protecting Circuits Against Hold Time Violations -- Padding Efficiency Of the Proposed Padding Algorithm -- Final Remarks.
000695686 506__ $$aAccess limited to authorized users.
000695686 520__ $$aThis book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements. The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.
000695686 588__ $$aDescription based on online resource; title from PDF title page (SpringerLink, viewed October 7, 2013).
000695686 650_0 $$aIntegrated circuits$$xDesign and construction.
000695686 650_0 $$aContinuous-time filters.
000695686 7001_ $$aWirth, Gilson,$$eauthor.
000695686 7001_ $$aReis, Ricardo A. L.$$q(Ricardo Augusto da Luz),$$eauthor.
000695686 85280 $$bebk$$hSpringerLink
000695686 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://dx.doi.org/10.1007/978-94-007-2427-3$$zOnline Access
000695686 909CO $$ooai:library.usi.edu:695686$$pGLOBAL_SET
000695686 980__ $$aEBOOK
000695686 980__ $$aBIB
000695686 982__ $$aEbook
000695686 983__ $$aOnline
000695686 994__ $$a92$$bISE