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Protecting chips against hold time violations due to variability [electronic resource] / Gustavo Neuberger, Gilson Wirth, Ricardo Reis.

Neuberger, Gustavo, author.; Wirth, Gilson, author.; Reis, Ricardo A. L. (Ricardo Augusto da Luz), author.
2013
TK7874.65
Available Online
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Title
Protecting chips against hold time violations due to variability [electronic resource] / Gustavo Neuberger, Gilson Wirth, Ricardo Reis.
Author
Neuberger, Gustavo, author.
ISBN
9789400724273 electronic book
9400724276 electronic book
9789400724266
DOI
https://doi.org/10.1007/978-94-007-2427-3
Published
New York : Springer, [2013?]
Copyright
©2014
Language
English
Description
1 online resource (xi, 107 pages) : illustrations (some color)
Item Number
10.1007/978-94-007-2427-3 doi
Call Number
TK7874.65
Dewey Decimal Classification
621.3815
Summary
This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements. The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.
Bibliography, etc. Note
Includes bibliographical references.
Access Note
Access limited to authorized users.
Source of Description
Description based on online resource; title from PDF title page (SpringerLink, viewed October 7, 2013).
Added Author
Wirth, Gilson, author.
Reis, Ricardo A. L. (Ricardo Augusto da Luz), author.
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Introduction, Process Variations and Flip-Flops
Process Variability
Flip-Flops and Hold Time Violations
Circuits Under Test
Measurement Circuits
Experimental Results
Systematic and Random Variablility
Normality Tests
Probability of Hold Time Violations
Protecting Circuits Against Hold Time Violations
Padding Efficiency Of the Proposed Padding Algorithm
Final Remarks.

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