Stochastic process variation in deep-submicron CMOS [electronic resource] : circuits and algorithms / Amir Zjajo.
Zjajo, Amir, author.
2014
TK7871.99.M44
Available Online

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Title Stochastic process variation in deep-submicron CMOS [electronic resource] : circuits and algorithms / Amir Zjajo.
Author Zjajo, Amir, author.
ISBN 9789400777811 electronic book
9400777817 electronic book
9789400777804
DOI https://doi.org/10.1007/978-94-007-7781-1
Published Dordrecht : Springer, 2014.
Language English
Description 1 online resource (xix, 192 pages) : illustrations.
Item Number 10.1007/978-94-007-7781-1 doi
Call Number TK7871.99.M44
Dewey Decimal Classification 621.3815/2
Summary One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.
Bibliography, etc. Note Includes bibliographical references and index.
Access Note Access limited to authorized users.
Source of Description Description based on online resource; title from PDF title page (SpringerLink, viewed November 18, 2013).
Series Springer series in advanced microelectronics ; v.48. 1437-0387
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Record Appears in Online Resources > Ebooks
All Resources
Random Process Variation in Deep-Submicron CMOS
Electronic Noise in Deep-Submicron CMOS
Temperature Effects in Deep-Submicron CMOS
Circuit Solutions
Conclusions and Recommendations.

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