Source-synchronous networks-on-chip [electronic resource] : circuit and architectural interconnect modeling / Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra.
2014
TK5105.546
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Title
Source-synchronous networks-on-chip [electronic resource] : circuit and architectural interconnect modeling / Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra.
Author
Mandal, Ayan, author.
ISBN
9781461494058 electronic book
1461494052 electronic book
9781461494041
1461494052 electronic book
9781461494041
Published
New York : Springer, 2014.
Language
English
Description
1 online resource (xiii, 143 pages) : illustrations (some color)
Item Number
10.1007/978-1-4614-9405-8 doi
Call Number
TK5105.546
Dewey Decimal Classification
621.3815/31
Summary
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. Describes novel methods for high-speed network-on-chip (NoC) design; Enables readers to understand NoC design from both circuit and architectural levels; Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.
Bibliography, etc. Note
Includes bibliographical references and index.
Access Note
Access limited to authorized users.
Source of Description
Description based on online resource; title from PDF title page (SpringerLink, viewed November 18, 2013).
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Table of Contents
Clock Distribution for fast Networks-on-Chip
Fast Network-on-Chip Design
Fast On-Chip Data transfer using Sinusoid Signals
Conclusion and Future Work.
Fast Network-on-Chip Design
Fast On-Chip Data transfer using Sinusoid Signals
Conclusion and Future Work.