Pipelined multiprocessor system-on-chip for multimedia [electronic resource] / Haris Javaid, Sri Parameswaran.

Pipelined multiprocessor system-on-chip for multimedia [electronic resource] / Haris Javaid, Sri Parameswaran.

9783319011134 electronic book
3319011138 electronic book
9783319011127

Cham : Springer, 2014.

English

1 online resource (viii, 169 pages) : illustrations (some color)

10.1007/978-3-319-01113-4 doi

TK7895.E42

621.3815

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers.

Includes bibliographical references and index.

Access limited to authorized users.

Description based on online resource; title from PDF title page (SpringerLink, viewed December 3, 2013).

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