High performance multi-channel high-speed I/O circuits [electronic resource] / Taehyoun Oh, Ramesh Harjani.
Taehyoun, Oh, author.; Harjani, Ramesh, 1959-, author.
2013
TK5102.5
Available Online

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Title
High performance multi-channel high-speed I/O circuits [electronic resource] / Taehyoun Oh, Ramesh Harjani.
Author
Taehyoun, Oh, author.
ISBN
9781461449638 electronic book
1461449634 electronic book
9781461449621
DOI
https://doi.org/10.1007/978-1-4614-4963-8
Published
New York : Springer, 2013.
Language
English
Description
1 online resource.
Item Number
10.1007/978-1-4614-4963-8 doi
Call Number
TK5102.5
Dewey Decimal Classification
621.38224
Summary
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits; Includes critical background knowledge related to channel ISI equalization circuits; Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems.
Bibliography, etc. Note
Includes bibliographical references.
Access Note
Access limited to authorized users.
Source of Description
Description based on print version record.
Added Author
Harjani, Ramesh, 1959-, author.
Series
Analog circuits and signal processing series.
Available in Other Form
High performance multi-channel high-speed I/O circuits
Linked Resources
Online Access
Record Appears in
Online Resources > Ebooks
All Resources
2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process
4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process
Adaptive XTCR, AGC, and Adaptive DFE Loop
Research Summary & Contributions
Appendix A: Noise Analysis
Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os ( 4)
Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter
Appendix D: Line Mismatch Sensitivity
Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench
Appendix F: Bandwidth Improvement by Technology Scaling.

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