000697206 000__ 02313cam\a2200457Ii\4500 000697206 001__ 697206 000697206 005__ 20230306135727.0 000697206 006__ m\\\\\o\\d\\\\\\\\ 000697206 007__ cr\cnu---unuuu 000697206 008__ 140131s2014\\\\sz\\\\\\ob\\\\001\0\eng\d 000697206 020__ $$z9783319036588 000697206 020__ $$z3319036580 000697206 020__ $$a9783319036595 $$qelectronic book 000697206 020__ $$a3319036599 $$qelectronic book 000697206 035__ $$aSP(OCoLC)ocn869553702 000697206 035__ $$aSP(OCoLC)869553702 000697206 040__ $$aN$T$$beng$$erda$$epn$$cN$T$$dYDXCP$$dGW5XE$$dGGVRL$$dCOO 000697206 049__ $$aISEA 000697206 050_4 $$aTK7872.P38$$bB73 2014eb 000697206 08204 $$a621.3815/364$$223 000697206 1001_ $$aBrandonisio, Francesco,$$eauthor. 000697206 24510 $$aNoise-shaping all-digital phase-locked loops$$h[electronic resource] :$$bmodeling, simulation, analysis and design /$$cFrancesco Brandonisio, Michael Peter Kennedy. 000697206 264_1 $$aCham :$$bSpringer,$$c[2014] 000697206 300__ $$a1 online resource 000697206 336__ $$atext$$btxt$$2rdacontent 000697206 337__ $$acomputer$$bc$$2rdamedia 000697206 338__ $$aonline resource$$bcr$$2rdacarrier 000697206 4901_ $$aAnalog circuits and signal processing 000697206 504__ $$aIncludes bibliographical references and index. 000697206 5050_ $$a1. Introduction -- 2. Phase digitization in all-digital PLLs -- 3. A unifying framework for TDC architectures -- 4. Analytical predictions of phase noise in ADPLLs -- 5. Advantages of noise shaping and dither -- 6. Efficient modeling and simulation of accumulator-based ADPLLs -- 7. Modelling and estimating phase noise with Matlab. 000697206 506__ $$aAccess limited to authorized users. 000697206 520__ $$aThis book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. 000697206 588__ $$aDescription based on print version record. 000697206 650_0 $$aPhase-locked loops. 000697206 7001_ $$aKennedy, Michael Peter,$$eauthor. 000697206 77608 $$iPrint version:$$tNoise-shaping All-digital Phase-locked Loops$$z9783319036588$$w(OCoLC)865493074 000697206 830_0 $$aAnalog circuits and signal processing series. 000697206 85280 $$bebk$$hSpringerLink 000697206 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://dx.doi.org/10.1007/978-3-319-03659-5$$zOnline Access 000697206 909CO $$ooai:library.usi.edu:697206$$pGLOBAL_SET 000697206 980__ $$aEBOOK 000697206 980__ $$aBIB 000697206 982__ $$aEbook 000697206 983__ $$aOnline 000697206 994__ $$a92$$bISE