A pipelined multi-core MIPS machine [electronic resource] : hardware implementation and correctness proof / Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul (Eds.).

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A pipelined multi-core MIPS machine [electronic resource] : hardware implementation and correctness proof / Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul (Eds.).

9783319139067 electronic book
3319139061 electronic book
9783319139050
3319139053

Cham : Springer, [2014]

©2014

English

1 online resource

QA76.9.A73 P57 2014eb

004.2/2

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

Includes bibliographical references and index.

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Lecture notes in computer science ; 9000.
LNCS sublibrary. SL 1, Theoretical computer science and general issues.

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