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Title
Designing 2D and 3D network-on-chip architectures [electronic resource] / Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch.
ISBN
9781461442745 electronic book
1461442745 electronic book
9781461442738
Published
New York : Springer, [2014]
Language
English
Description
1 online resource (xiii, 265 pages) : illustrations (some color)
Item Number
10.1007/978-1-4614-4274-5 doi
Call Number
TK5105.546
Dewey Decimal Classification
006.2/2
Summary
This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies.
Bibliography, etc. Note
Includes bibliographical references.
Access Note
Access limited to authorized users.
Source of Description
Description based on online resource; title from PDF title page (SpringerLink, viewed October 14, 2013).
Network-on-Chip Design Methodology. Network-on-Chip Technology: A Paradigm Shift
NoC Modeling and Topology Exploration
Communication Architecture
Power and Thermal Effects and Management
NoC-based System Integration
NoC Verification and Testing
The Spidergon STNoC
Middleware Memory Management in NoC
On Designing 3-D Platforms
The SYSMANTIC NoC Design and Prototyping Framework
Suggested Projects. Projects on Network-on Chip.
