TY  - GEN
N2  - This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems.? It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time.? Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifyin.
DO  - 10.1007/978-3-319-08753-5
DO  - doi
AB  - This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems.? It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time.? Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifyin.
T1  - Out-of-order parallel discrete event simulation for electronic system-level design
AU  - Chen, Weiwei,
CN  - TK7895.E42
ID  - 723393
KW  - Systems on a chip
SN  - 9783319087535
SN  - 3319087533
TI  - Out-of-order parallel discrete event simulation for electronic system-level design
LK  - https://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-08753-5
UR  - https://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-08753-5
ER  -