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000723393 019__ $$a894170155
000723393 020__ $$a9783319087535$$qelectronic book
000723393 020__ $$a3319087533$$qelectronic book
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000723393 0247_ $$a10.1007/978-3-319-08753-5$$2doi
000723393 035__ $$aSP(OCoLC)ocn885262313
000723393 035__ $$aSP(OCoLC)885262313$$z(OCoLC)894170155
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000723393 049__ $$aISEA
000723393 050_4 $$aTK7895.E42
000723393 08204 $$a621.3815$$223
000723393 1001_ $$aChen, Weiwei,$$eauthor.
000723393 24510 $$aOut-of-order parallel discrete event simulation for electronic system-level design$$h[electronic resource] /$$cWeiwei Chen ; foreword by Rainer Dömer.
000723393 264_1 $$aCham :$$bSpringer,$$c[2014]
000723393 264_4 $$c©2015
000723393 300__ $$a1 online resource (xix, 145 pages) :$$billustrations.
000723393 336__ $$atext$$btxt$$2rdacontent
000723393 337__ $$acomputer$$bc$$2rdamedia
000723393 338__ $$aonline resource$$bcr$$2rdacarrier
000723393 504__ $$aIncludes bibliographical references and index.
000723393 5050_ $$aForeword; Preface; Acknowledgments; Contents; Acronyms; 1 Introduction; 1.1 System-Level Design; 1.1.1 Levels of Abstraction; 1.1.2 The Y-Chart; 1.1.3 System-Level Design Methodologies; 1.1.4 Electronic System-Level Design Process; 1.2 Validation and Simulation; 1.2.1 Language Support for System-Level Design; 1.2.2 System Simulation Approaches; 1.2.3 Discrete Event Simulation; 1.3 Goals; 1.4 Overview; 1.5 Related Work; 1.5.1 The SpecC Language; 1.5.2 The SystemC Language; 1.5.3 The System-on-Chip Environment Design Flow; 1.5.4 Multicore Technology and Multithreaded Programming
000723393 5058_ $$a1.5.5 Efficient Model Validation and Simulation2 The ConcurrenC Model of Computation; 2.1 Motivation; 2.2 Models of Computation; 2.3 ConcurrenC MoC; 2.3.1 Relationship to C-based SLDLs; 2.3.2 ConcurrenC Features; 2.3.3 Communication Channel Library; 2.3.4 Relationship to KPN and SDF; 2.4 Case Study; 3 Synchronous Parallel Discrete Event Simulation; 3.1 Traditional Discrete Event Simulation; 3.2 SLDL Multithreading Semantics; 3.2.1 Cooperative Multithreading in SystemC; 3.2.2 Pre-emptive Multithreading in SpecC; 3.3 Synchronous Parallel Discrete Event Simulation
000723393 5058_ $$a3.4 Synchronization for Multicore Parallel Simulation3.4.1 Protecting Scheduling Resources; 3.4.2 Protecting Communication; 3.4.3 Channel Locking Scheme ; 3.4.4 Automatic Code Instrumentation for Communication Protection ; 3.5 Implementation Optimization for Multicore Simulation; 3.6 Experiments and Results; 3.6.1 Case Study on a H.264 Video Decoder; 3.6.2 Case Study on a JPEG Encoder ; 4 Out-of-Order Parallel Discrete Event Simulation; 4.1 Motivation; 4.2 Out-of-Order Parallel Discrete Event Simulation; 4.2.1 Notations; 4.2.2 Out-of-Order PDES Scheduling Algorithm
000723393 5058_ $$a4.3 Out-of-Order PDES Conflict Analysis4.3.1 Thread Segments and Segment Graph; 4.3.2 Static Conflict Analysis; 4.3.3 Dynamic Conflict Detection; 4.4 Experimental Results; 4.4.1 An Abstract Model of a DVD Player; 4.4.2 A JPEG Encoder Model; 4.4.3 A Detailed H.264 Decoder Model; 5 Optimized Out-of-Order Parallel Discrete Event Simulation; 5.1 Optimized Compiler Using Instance Isolation; 5.1.1 Motivation; 5.1.2 Instance Isolation Without Code Duplication; 5.1.3 Definitions for the Optimized Static Conflict Analysis; 5.1.4 Algorithm for Static Conflict Analysis; 5.1.5 Experimental Results
000723393 5058_ $$a5.2 Optimized Scheduling Using Predictions5.2.1 State Prediction to Avoid False Conflicts; 5.2.2 Static Prediction Analysis; 5.2.3 Out-of-Order PDES Scheduling with Predictions; 5.2.4 Optimized Out-of-Order PDES Scheduling Conflict Checking with a Combined Prediction Table; 5.2.5 Experimental Results; 6 Comparison and Outlook; 6.1 Experimental Setup; 6.1.1 Experimental Environment Setup; 6.1.2 The Parallel Benchmark Models; 6.1.3 The Embedded Applications; 6.2 Parallel Discrete Event Simulation Overlook; 7 Utilizing the Parallel Simulation Infrastructure; 7.1 Introduction
000723393 506__ $$aAccess limited to authorized users.
000723393 520__ $$aThis book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems.? It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time.? Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifyin.
000723393 588__ $$aDescription based on online resource; title from PDF title page (SpringerLink, viewed August 5, 2014).
000723393 588__ $$aDescription based on print version record.
000723393 650_0 $$aSystems on a chip$$xDesign.
000723393 77608 $$iPrint version:$$aChen, Weiwei$$tOut-of-order Parallel Discrete Event Simulation for Electronic System-level Design$$dDordrecht : Springer,c2014$$z9783319087528
000723393 852__ $$bebk
000723393 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-08753-5$$zOnline Access$$91397441.1
000723393 909CO $$ooai:library.usi.edu:723393$$pGLOBAL_SET
000723393 980__ $$aEBOOK
000723393 980__ $$aBIB
000723393 982__ $$aEbook
000723393 983__ $$aOnline
000723393 994__ $$a92$$bISE