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000723881 019__ $$a908083122
000723881 020__ $$a9783319019970$$qelectronic book
000723881 020__ $$a331901997X$$qelectronic book
000723881 020__ $$z9783319019963
000723881 0247_ $$a10.1007/978-3-319-01997-0$$2doi
000723881 035__ $$aSP(OCoLC)ocn894042300
000723881 035__ $$aSP(OCoLC)894042300$$z(OCoLC)908083122
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000723881 049__ $$aISEA
000723881 050_4 $$aTK7871.99.M44
000723881 08204 $$a621.3815$$223
000723881 1001_ $$aAlioto, Massimo,$$eauthor.
000723881 24510 $$aFlip-flop design in nanometer CMOS$$h[electronic resource] :$$bfrom high speed to low energy /$$cMassimo Alioto, Elio Consoli, Gaetano Palumbo.
000723881 264_1 $$aCham :$$bSpringer,$$c[2014]
000723881 264_4 $$c©2015
000723881 300__ $$a1 online resource (xv, 260 pages) :$$billustrations (some color)
000723881 336__ $$atext$$btxt$$2rdacontent
000723881 337__ $$acomputer$$bc$$2rdamedia
000723881 338__ $$aonline resource$$bcr$$2rdacarrier
000723881 504__ $$aIncludes bibliographical references and index.
000723881 5050_ $$aPreface; Contents; 1 The Logical Effort Method; 1.1An RC Model for the Delay of Logic Gates; 1.2The Logical Effort Model; 1.3Limitations of the Original Logical Effort Model; 1.4Basic Estimation of Logical Effort Parameters; 1.5Accurate Estimation of Parameters g and p; 1.5.1 Estimation of the Capacitance at Internal Nodes; 1.5.2 Elmore Delay; 1.5.3 Parameter Calibration; 1.5.4 Non-step Input; 1.6Multistage Logic Networks and Delay Minimization; 1.6.1 Path Parameters; 1.6.2 Optimized Design; 1.7Optimum Number of Stages; 1.8Extension of the Model to Non-static Gates
000723881 5058_ $$a1.8.1 Dynamic and Domino Gates with Keeper1.8.2 Logic with Transmission Gates and Pass-transistors; 1.9Nonlinearities and Need for Iterative Procedures; Appendix: Derivation of Logical Effort with a Transistor Current Source Model; 2 Design in the Energy-Delay Space; 2.1Energy Modeling; 2.2Energy-Delay Space Analysis and Hardware-Intensity; 2.2.1 The Energy-Efficient Curve; 2.2.2 Energy-Delay Metrics and Hardware Intensity; 2.2.3 Voltage Intensity and Generalization of the Sensitivity Criterion; 2.3Energy-Efficient Design of Digital Circuits; 2.3.1 The Role of the Input Capacitance
000723881 5058_ $$a2.3.2 Derivation of Design Space Bounds2.3.3 Simulation-Based Optimization of Small-Sized Circuits; 2.3.4 Nonlinear and Convex Optimization of Large Size Circuits; 2.4Design of Energy-Efficient Pipelined Systems; 2.4.1 Zyuban and Strenski's Hardware-Voltage Intensity Criteria; 2.4.2 Practical Guidelines to Design Energy-Efficient Pipelines; A.1. Appendix: Convex Optimization; 3 Clocked Storage Elements; 3.1...Clocking in Synchronous Digital Systems; 3.2...Features of the Clock Signal; 3.3...Clocked Storage Elements: Latches, Master -- Slave Flip-Flops and Pulsed Topologies
000723881 5058_ $$a3.4...Timing Parameters of Clocked Storage Elements3.4.1 Setup Time and Hold Time; 3.4.2 The Data Race-Through Issue; 3.4.3 Differences Between Master -- Slave and Pulsed FFs; 3.4.4 Latches; 3.5...Clock Uncertainties Absorption and Time Borrowing; 3.6...Energy Consumption in Flip-Flops; 3.6.1 Dynamic Energy Dissipation and Techniques for Its Reduction; 3.6.2 Glitches, Short-Circuit and Static Energy Dissipation; 3.7...Differential and Dual Edge-Triggered Topologies; 4 Flip-Flop Optimized Design; 4.1...A Comprehensive Design Approach; 4.2...Definition of Independent Design Variables: Step 1
000723881 5058_ $$a4.2.1 A Single Path4.2.2 Two Different Re-converging Paths; 4.2.3 A Bifurcating Path; 4.2.4 Other Cases; 4.3...Sizing of Dependent Design Variables: Step 2; 4.3.1 Clocked Precharge Transistors; 4.3.2 Keepers and Noise Immunity; 4.3.3 Feedback Paths; 4.3.4 Pulse Generators; 4.3.4.1 NAND Design; 4.3.4.2 Inverters Chain Design; 4.3.4.3 Different Pulse Generator Topologies; 4.3.5 IDVs and DDVs in SDFF First Stage; 4.4...Estimation of Design Space (IDVs) Bounds: Step 3; 4.5...Extrapolation of the Energy-Efficient Curve: Step 4; 4.6...A Complete Design Example: The SDFF as Case of Study
000723881 506__ $$aAccess limited to authorized users.
000723881 520__ $$aThis book offers a comprehensive treatment of Flip-Flop design, including nanometer effects and the consequent design tradeoffs for current and future VLSI systems. It examines more than 20 topologies, covering all relevant classes of circuits.
000723881 588__ $$aOnline resource; title from PDF title page (SpringerLink, viewed October 30, 2014).
000723881 650_0 $$aMetal oxide semiconductors, Complementary$$xDesign and construction.
000723881 650_0 $$aFlip chip technology.
000723881 650_0 $$aIntegrated circuits$$xVery large scale integration$$xDesign and construction.
000723881 7001_ $$aConsoli, Elio,$$eauthor.
000723881 7001_ $$aPalumbo, Gaetano,$$eauthor.
000723881 77608 $$iPrint version:$$aAlioto, Massimo$$tFlip-Flop Design in Nanometer CMOS : From High Speed to Low Energy$$dCham : Springer International Publishing,c2014$$z9783319019963
000723881 852__ $$bebk
000723881 85640 $$3SpringerLink$$uhttps://univsouthin.idm.oclc.org/login?url=http://link.springer.com/10.1007/978-3-319-01997-0$$zOnline Access$$91397441.1
000723881 909CO $$ooai:library.usi.edu:723881$$pGLOBAL_SET
000723881 980__ $$aEBOOK
000723881 980__ $$aBIB
000723881 982__ $$aEbook
000723881 983__ $$aOnline
000723881 994__ $$a92$$bISE